Lines Matching defs:val
461 * @val: cyclic buffer for registers value
467 u32 val[UFS_EVENT_HIST_LENGTH];
1201 #define ufsmcq_writel(hba, val, reg) \
1202 writel((val), (hba)->mcq_base + (reg))
1206 #define ufsmcq_writelx(hba, val, reg) \
1207 writel_relaxed((val), (hba)->mcq_base + (reg))
1211 #define ufshcd_writel(hba, val, reg) \
1212 writel((val), (hba)->mmio_base + (reg))
1220 * @val: actual value to write
1223 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
1229 tmp |= (val & mask);
1244 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val);
1249 void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i);