Lines Matching refs:status
61 #define SSB_CHIPCO_OTPS 0x0010 /* OTP status */
189 #define SSB_CHIPCO_CLKCTLST 0x01E0 /* Clock control and status (rev >= 20) */
231 #define SSB_CHIPCO_PMU_STAT 0x0608 /* PMU status */
233 #define SSB_CHIPCO_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
237 #define SSB_CHIPCO_PMU_RES_STAT 0x060C /* PMU res status */
411 #define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
412 ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
414 #define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
415 (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
416 #define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
417 (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
419 ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
495 /** Flash-specific control/status values */
590 u32 status;