Lines Matching defs:dpcd
47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
107 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
109 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
113 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
115 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
119 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
121 return dpcd[DP_DPCD_REV] >= 0x11 &&
122 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
126 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
128 return dpcd[DP_DPCD_REV] >= 0x11 &&
129 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
133 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
135 return dpcd[DP_DPCD_REV] >= 0x12 &&
136 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
140 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
142 return dpcd[DP_DPCD_REV] >= 0x11 ||
143 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5;
147 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
149 return dpcd[DP_DPCD_REV] >= 0x14 &&
150 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
154 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
156 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
161 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
163 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
217 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
219 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
223 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
225 return dpcd[DP_EDP_CONFIGURATION_CAP] &
231 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
233 return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
491 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
504 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
506 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
508 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
511 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
513 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
516 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
519 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
522 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
524 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
527 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
531 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
536 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
540 const u8 *dpcd,
545 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
550 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
553 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
752 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
774 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],