Lines Matching refs:wdt
3 * drivers/char/watchdog/sp805-wdt.c
36 #define MODULE_NAME "sp805-wdt"
57 * struct sp805_wdt: sp805 wdt device structure
60 * @base: base address of wdt
61 * @clk: (optional) clock structure of wdt
63 * @adev: amba device structure of wdt
64 * @status: current status of wdt
82 /* returns true if wdt is running; otherwise returns false */
85 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
86 u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL);
94 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
97 rate = wdt->rate;
110 spin_lock(&wdt->lock);
111 wdt->load_val = load;
114 spin_unlock(&wdt->lock);
122 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
125 spin_lock(&wdt->lock);
126 load = readl_relaxed(wdt->base + WDTVALUE);
129 if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
130 load += wdt->load_val + 1;
131 spin_unlock(&wdt->lock);
133 return div_u64(load, wdt->rate);
139 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
141 writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
142 writel_relaxed(0, wdt->base + WDTCONTROL);
143 writel_relaxed(0, wdt->base + WDTLOAD);
144 writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
147 readl_relaxed(wdt->base + WDTLOCK);
154 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
159 ret = clk_prepare_enable(wdt->clk);
161 dev_err(&wdt->adev->dev, "clock enable fail");
166 spin_lock(&wdt->lock);
168 writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
169 writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
170 writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
173 writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base +
176 writel_relaxed(LOCK, wdt->base + WDTLOCK);
179 readl_relaxed(wdt->base + WDTLOCK);
180 spin_unlock(&wdt->lock);
199 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
201 spin_lock(&wdt->lock);
203 writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
204 writel_relaxed(0, wdt->base + WDTCONTROL);
205 writel_relaxed(LOCK, wdt->base + WDTLOCK);
208 readl_relaxed(wdt->base + WDTLOCK);
209 spin_unlock(&wdt->lock);
211 clk_disable_unprepare(wdt->clk);
234 struct sp805_wdt *wdt;
238 wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL);
239 if (!wdt) {
244 wdt->base = devm_ioremap_resource(&adev->dev, &adev->res);
245 if (IS_ERR(wdt->base))
246 return PTR_ERR(wdt->base);
255 wdt->clk = devm_clk_get_optional(&adev->dev, NULL);
256 if (IS_ERR(wdt->clk))
257 return dev_err_probe(&adev->dev, PTR_ERR(wdt->clk), "Clock not found\n");
259 wdt->rate = clk_get_rate(wdt->clk);
260 if (!wdt->rate)
261 wdt->rate = rate;
262 if (!wdt->rate) {
267 wdt->adev = adev;
268 wdt->wdd.info = &wdt_info;
269 wdt->wdd.ops = &wdt_ops;
270 wdt->wdd.parent = &adev->dev;
272 spin_lock_init(&wdt->lock);
273 watchdog_set_nowayout(&wdt->wdd, nowayout);
274 watchdog_set_drvdata(&wdt->wdd, wdt);
275 watchdog_set_restart_priority(&wdt->wdd, 128);
276 watchdog_stop_on_unregister(&wdt->wdd);
282 wdt->wdd.timeout = DEFAULT_TIMEOUT;
283 watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
284 wdt_setload(&wdt->wdd, wdt->wdd.timeout);
287 * If HW is already running, enable/reset the wdt and set the running
288 * bit to tell the wdt subsystem
290 if (wdt_is_running(&wdt->wdd)) {
291 wdt_enable(&wdt->wdd);
292 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
295 watchdog_stop_on_reboot(&wdt->wdd);
296 ret = watchdog_register_device(&wdt->wdd);
299 amba_set_drvdata(adev, wdt);
311 struct sp805_wdt *wdt = amba_get_drvdata(adev);
313 watchdog_unregister_device(&wdt->wdd);
314 watchdog_set_drvdata(&wdt->wdd, NULL);
319 struct sp805_wdt *wdt = dev_get_drvdata(dev);
321 if (watchdog_active(&wdt->wdd))
322 return wdt_disable(&wdt->wdd);
329 struct sp805_wdt *wdt = dev_get_drvdata(dev);
331 if (watchdog_active(&wdt->wdd))
332 return wdt_enable(&wdt->wdd);