Lines Matching refs:wdt
267 { .compatible = "samsung,s3c2410-wdt",
269 { .compatible = "samsung,s3c6410-wdt",
271 { .compatible = "samsung,exynos5250-wdt",
273 { .compatible = "samsung,exynos5420-wdt",
275 { .compatible = "samsung,exynos7-wdt",
277 { .compatible = "samsung,exynos850-wdt",
279 { .compatible = "samsung,exynosautov9-wdt",
288 .name = "s3c2410-wdt",
297 static inline unsigned long s3c2410wdt_get_freq(struct s3c2410_wdt *wdt)
299 return clk_get_rate(wdt->src_clk ? wdt->src_clk : wdt->bus_clk);
302 static inline unsigned int s3c2410wdt_max_timeout(struct s3c2410_wdt *wdt)
304 const unsigned long freq = s3c2410wdt_get_freq(wdt);
310 static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask)
312 const u32 mask_val = BIT(wdt->drv_data->mask_bit);
316 ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg,
319 dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
324 static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask)
326 const u32 mask_val = BIT(wdt->drv_data->mask_bit);
327 const bool val_inv = wdt->drv_data->mask_reset_inv;
331 ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg,
334 dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
339 static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en)
341 const u32 mask_val = BIT(wdt->drv_data->cnt_en_bit);
345 ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->cnt_en_reg,
348 dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
353 static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
357 if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) {
358 ret = s3c2410wdt_disable_wdt_reset(wdt, !en);
363 if (wdt->drv_data->quirks & QUIRK_HAS_PMU_MASK_RESET) {
364 ret = s3c2410wdt_mask_wdt_reset(wdt, !en);
369 if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CNT_EN) {
370 ret = s3c2410wdt_enable_counter(wdt, en);
380 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
383 spin_lock_irqsave(&wdt->lock, flags);
384 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
385 spin_unlock_irqrestore(&wdt->lock, flags);
390 static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
394 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
396 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
401 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
404 spin_lock_irqsave(&wdt->lock, flags);
405 __s3c2410wdt_stop(wdt);
406 spin_unlock_irqrestore(&wdt->lock, flags);
414 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
417 spin_lock_irqsave(&wdt->lock, flags);
419 __s3c2410wdt_stop(wdt);
421 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
432 dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
433 wdt->count, wtcon);
435 writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
436 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
437 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
438 spin_unlock_irqrestore(&wdt->lock, flags);
446 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
447 unsigned long freq = s3c2410wdt_get_freq(wdt);
458 dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n",
470 dev_err(wdt->dev, "timeout %d too big\n", timeout);
475 dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n",
479 wdt->count = count;
482 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
486 writel(count, wdt->reg_base + S3C2410_WTDAT);
487 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
497 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
498 void __iomem *wdt_base = wdt->reg_base;
545 struct s3c2410_wdt *wdt = platform_get_drvdata(param);
547 dev_info(wdt->dev, "watchdog timer expired (irq)\n");
549 s3c2410wdt_keepalive(&wdt->wdt_device);
551 if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG)
552 writel(0x1, wdt->reg_base + S3C2410_WTCLRINT);
557 static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
562 if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_RST_STAT))
565 ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
567 dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
568 else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
575 s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
613 wdt->drv_data = variant;
625 struct s3c2410_wdt *wdt;
630 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
631 if (!wdt)
634 wdt->dev = dev;
635 spin_lock_init(&wdt->lock);
636 wdt->wdt_device = s3c2410_wdd;
638 ret = s3c2410_get_wdt_drv_data(pdev, wdt);
642 if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
643 wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
645 if (IS_ERR(wdt->pmureg))
646 return dev_err_probe(dev, PTR_ERR(wdt->pmureg),
655 wdt->reg_base = devm_platform_ioremap_resource(pdev, 0);
656 if (IS_ERR(wdt->reg_base))
657 return PTR_ERR(wdt->reg_base);
659 wdt->bus_clk = devm_clk_get_enabled(dev, "watchdog");
660 if (IS_ERR(wdt->bus_clk))
661 return dev_err_probe(dev, PTR_ERR(wdt->bus_clk), "failed to get bus clock\n");
667 wdt->src_clk = devm_clk_get_optional_enabled(dev, "watchdog_src");
668 if (IS_ERR(wdt->src_clk))
669 return dev_err_probe(dev, PTR_ERR(wdt->src_clk), "failed to get source clock\n");
671 wdt->wdt_device.min_timeout = 1;
672 wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt);
674 watchdog_set_drvdata(&wdt->wdt_device, wdt);
679 watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev);
680 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
681 wdt->wdt_device.timeout);
683 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
697 watchdog_set_nowayout(&wdt->wdt_device, nowayout);
698 watchdog_set_restart_priority(&wdt->wdt_device, 128);
700 wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
701 wdt->wdt_device.parent = dev;
712 s3c2410wdt_start(&wdt->wdt_device);
713 set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status);
715 s3c2410wdt_stop(&wdt->wdt_device);
718 ret = devm_watchdog_register_device(dev, &wdt->wdt_device);
722 ret = s3c2410wdt_enable(wdt, true);
726 ret = devm_add_action_or_reset(dev, s3c2410wdt_wdt_disable_action, wdt);
730 platform_set_drvdata(pdev, wdt);
734 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
746 struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
748 s3c2410wdt_enable(wdt, false);
749 s3c2410wdt_stop(&wdt->wdt_device);
755 struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
758 wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
759 wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
761 ret = s3c2410wdt_enable(wdt, false);
766 s3c2410wdt_stop(&wdt->wdt_device);
774 struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
777 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
778 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
779 writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
781 ret = s3c2410wdt_enable(wdt, true);
786 (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
799 .name = "s3c2410-wdt",