Lines Matching defs:mask_bit
88 * new SoCs have CLUSTERx_NONCPU_INT_EN register, which 'mask_bit' value is
97 * register. If 'mask_bit' bit is set, PMU will disable WDT reset when
142 * @mask_bit: Bit number for the watchdog timer in the disable register and the
156 int mask_bit;
191 .mask_bit = 20,
201 .mask_bit = 0,
211 .mask_bit = 23,
220 .mask_bit = 2,
232 .mask_bit = 2,
244 .mask_bit = 2,
256 .mask_bit = 2,
312 const u32 mask_val = BIT(wdt->drv_data->mask_bit);
326 const u32 mask_val = BIT(wdt->drv_data->mask_bit);