Lines Matching refs:ctrl

76 	struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
79 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
81 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
88 struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
91 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
93 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
100 struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
102 iowrite32(OTTO_WDT_CNTR_PING, ctrl->base + OTTO_WDT_REG_CNTR);
107 static int otto_wdt_tick_ms(struct otto_wdt_ctrl *ctrl, int prescale)
109 return DIV_ROUND_CLOSEST(1 << (25 + prescale), ctrl->clk_rate_khz);
126 struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
142 tick_ms = otto_wdt_tick_ms(ctrl, prescale);
151 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
158 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
161 ctrl->wdev.timeout = timeout_ms / 1000;
164 ctrl->wdev.pretimeout = pretimeout_ms / 1000;
182 struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
186 disable_irq(ctrl->irq_phase1);
202 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
204 mdelay(3 * otto_wdt_tick_ms(ctrl, 0));
211 struct otto_wdt_ctrl *ctrl = dev_id;
213 iowrite32(OTTO_WDT_INTR_PHASE_1, ctrl->base + OTTO_WDT_REG_INTR);
214 dev_crit(ctrl->dev, "phase 1 timeout\n");
215 watchdog_notify_pretimeout(&ctrl->wdev);
238 static int otto_wdt_probe_clk(struct otto_wdt_ctrl *ctrl)
242 clk = devm_clk_get_enabled(ctrl->dev, NULL);
244 return dev_err_probe(ctrl->dev, PTR_ERR(clk), "Failed to get clock\n");
246 ctrl->clk_rate_khz = clk_get_rate(clk) / 1000;
247 if (ctrl->clk_rate_khz == 0)
248 return dev_err_probe(ctrl->dev, -ENXIO, "Failed to get clock rate\n");
253 static int otto_wdt_probe_reset_mode(struct otto_wdt_ctrl *ctrl)
256 const struct fwnode_handle *node = ctrl->dev->fwnode;
281 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
284 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
292 struct otto_wdt_ctrl *ctrl;
296 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
297 if (!ctrl)
300 ctrl->dev = dev;
301 ctrl->base = devm_platform_ioremap_resource(pdev, 0);
302 if (IS_ERR(ctrl->base))
303 return PTR_ERR(ctrl->base);
307 ctrl->base + OTTO_WDT_REG_INTR);
308 iowrite32(OTTO_WDT_CTRL_DEFAULT, ctrl->base + OTTO_WDT_REG_CTRL);
310 ret = otto_wdt_probe_clk(ctrl);
314 ctrl->irq_phase1 = platform_get_irq_byname(pdev, "phase1");
315 if (ctrl->irq_phase1 < 0)
316 return ctrl->irq_phase1;
318 ret = devm_request_irq(dev, ctrl->irq_phase1, otto_wdt_phase1_isr, 0,
319 "realtek-otto-wdt", ctrl);
323 ret = otto_wdt_probe_reset_mode(ctrl);
327 ctrl->wdev.parent = dev;
328 ctrl->wdev.info = &otto_wdt_info;
329 ctrl->wdev.ops = &otto_wdt_ops;
335 ctrl->wdev.min_timeout = 2;
336 max_tick_ms = otto_wdt_tick_ms(ctrl, OTTO_WDT_PRESCALE_MAX);
337 ctrl->wdev.max_hw_heartbeat_ms = max_tick_ms * OTTO_WDT_TIMEOUT_TICKS_MAX;
338 ctrl->wdev.timeout = min(30U, ctrl->wdev.max_hw_heartbeat_ms / 1000);
340 watchdog_set_drvdata(&ctrl->wdev, ctrl);
341 watchdog_init_timeout(&ctrl->wdev, 0, dev);
342 watchdog_stop_on_reboot(&ctrl->wdev);
343 watchdog_set_restart_priority(&ctrl->wdev, 128);
345 ret = otto_wdt_determine_timeouts(&ctrl->wdev, ctrl->wdev.timeout, 1);
349 return devm_watchdog_register_device(dev, &ctrl->wdev);