Lines Matching defs:lpc18xx_wdt
63 struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
70 spin_lock_irqsave(&lpc18xx_wdt->lock, flags);
71 writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
72 writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
73 spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags);
80 struct lpc18xx_wdt_dev *lpc18xx_wdt = from_timer(lpc18xx_wdt, t, timer);
81 struct watchdog_device *wdt_dev = &lpc18xx_wdt->wdt_dev;
86 mod_timer(&lpc18xx_wdt->timer, jiffies +
96 struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
98 lpc18xx_wdt_timer_feed(&lpc18xx_wdt->timer);
103 static void __lpc18xx_wdt_set_timeout(struct lpc18xx_wdt_dev *lpc18xx_wdt)
107 val = DIV_ROUND_UP(lpc18xx_wdt->wdt_dev.timeout * lpc18xx_wdt->clk_rate,
109 writel(val, lpc18xx_wdt->base + LPC18XX_WDT_TC);
115 struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
117 lpc18xx_wdt->wdt_dev.timeout = new_timeout;
118 __lpc18xx_wdt_set_timeout(lpc18xx_wdt);
125 struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
128 val = readl(lpc18xx_wdt->base + LPC18XX_WDT_TV);
129 return (val * LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate;
134 struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
137 if (timer_pending(&lpc18xx_wdt->timer))
138 del_timer(&lpc18xx_wdt->timer);
140 val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD);
143 writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD);
158 struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
165 spin_lock_irqsave(&lpc18xx_wdt->lock, flags);
167 val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD);
170 writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD);
172 writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
173 writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
175 writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
176 writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
178 spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags);
202 struct lpc18xx_wdt_dev *lpc18xx_wdt;
205 lpc18xx_wdt = devm_kzalloc(dev, sizeof(*lpc18xx_wdt), GFP_KERNEL);
206 if (!lpc18xx_wdt)
209 lpc18xx_wdt->base = devm_platform_ioremap_resource(pdev, 0);
210 if (IS_ERR(lpc18xx_wdt->base))
211 return PTR_ERR(lpc18xx_wdt->base);
213 lpc18xx_wdt->reg_clk = devm_clk_get_enabled(dev, "reg");
214 if (IS_ERR(lpc18xx_wdt->reg_clk)) {
216 return PTR_ERR(lpc18xx_wdt->reg_clk);
219 lpc18xx_wdt->wdt_clk = devm_clk_get_enabled(dev, "wdtclk");
220 if (IS_ERR(lpc18xx_wdt->wdt_clk)) {
222 return PTR_ERR(lpc18xx_wdt->wdt_clk);
226 lpc18xx_wdt->clk_rate = clk_get_rate(lpc18xx_wdt->wdt_clk);
227 if (lpc18xx_wdt->clk_rate == 0) {
232 lpc18xx_wdt->wdt_dev.info = &lpc18xx_wdt_info;
233 lpc18xx_wdt->wdt_dev.ops = &lpc18xx_wdt_ops;
235 lpc18xx_wdt->wdt_dev.min_timeout = DIV_ROUND_UP(LPC18XX_WDT_TC_MIN *
236 LPC18XX_WDT_CLK_DIV, lpc18xx_wdt->clk_rate);
238 lpc18xx_wdt->wdt_dev.max_timeout = (LPC18XX_WDT_TC_MAX *
239 LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate;
241 lpc18xx_wdt->wdt_dev.timeout = min(lpc18xx_wdt->wdt_dev.max_timeout,
244 spin_lock_init(&lpc18xx_wdt->lock);
246 lpc18xx_wdt->wdt_dev.parent = dev;
247 watchdog_set_drvdata(&lpc18xx_wdt->wdt_dev, lpc18xx_wdt);
249 watchdog_init_timeout(&lpc18xx_wdt->wdt_dev, heartbeat, dev);
251 __lpc18xx_wdt_set_timeout(lpc18xx_wdt);
253 timer_setup(&lpc18xx_wdt->timer, lpc18xx_wdt_timer_feed, 0);
255 watchdog_set_nowayout(&lpc18xx_wdt->wdt_dev, nowayout);
256 watchdog_set_restart_priority(&lpc18xx_wdt->wdt_dev, 128);
258 platform_set_drvdata(pdev, lpc18xx_wdt);
260 watchdog_stop_on_reboot(&lpc18xx_wdt->wdt_dev);
261 return devm_watchdog_register_device(dev, &lpc18xx_wdt->wdt_dev);
266 struct lpc18xx_wdt_dev *lpc18xx_wdt = platform_get_drvdata(pdev);
269 del_timer_sync(&lpc18xx_wdt->timer);