Lines Matching refs:wd
215 struct fintek_wdt *wd = watchdog_get_drvdata(wdd);
218 wd->timer_val = DIV_ROUND_UP(timeout, 60);
219 wd->minutes_mode = true;
220 timeout = wd->timer_val * 60;
222 wd->timer_val = timeout;
223 wd->minutes_mode = false;
231 static int fintek_wdt_set_pulse_width(struct fintek_wdt *wd, unsigned int pw)
235 if (wd->type == f71868) {
242 wd->pulse_val = 0;
244 wd->pulse_val = 1;
246 wd->pulse_val = 2;
248 wd->pulse_val = 3;
254 wd->pulse_mode = pw;
261 struct fintek_wdt *wd = watchdog_get_drvdata(wdd);
264 err = superio_enter(wd->sioaddr);
267 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
269 if (wd->minutes_mode)
271 superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
275 superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
279 superio_outb(wd->sioaddr, F71808FG_REG_WD_TIME,
280 wd->timer_val);
282 superio_exit(wd->sioaddr);
289 struct fintek_wdt *wd = watchdog_get_drvdata(wdd);
298 err = superio_enter(wd->sioaddr);
301 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
304 switch (wd->type) {
307 superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT2, 3);
308 superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT3, 3);
314 superio_clear_bit(wd->sioaddr, SIO_REG_ROM_ADDR_SEL, 6);
315 superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT3, 4);
317 superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT1, 1);
324 superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT1, 4);
329 superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT1, 1);
334 superio_outb(wd->sioaddr, SIO_REG_MFUNCT3,
335 superio_inb(wd->sioaddr, SIO_REG_MFUNCT3) & 0xcf);
340 superio_clear_bit(wd->sioaddr, SIO_REG_CLOCK_SEL, 3);
342 superio_outb(wd->sioaddr, SIO_REG_TSI_LEVEL_SEL, 0x5f &
343 superio_inb(wd->sioaddr, SIO_REG_TSI_LEVEL_SEL));
348 superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT3, 5);
359 tmp = superio_inb(wd->sioaddr, SIO_F81866_REG_PORT_SEL);
362 superio_outb(wd->sioaddr, SIO_F81866_REG_PORT_SEL, tmp);
364 superio_clear_bit(wd->sioaddr, SIO_F81866_REG_GPIO1, 5);
376 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
377 superio_set_bit(wd->sioaddr, SIO_REG_ENABLE, 0);
379 if (wd->type == f81865 || wd->type == f81866 || wd->type == f81966)
380 superio_set_bit(wd->sioaddr, F81865_REG_WDO_CONF,
383 superio_set_bit(wd->sioaddr, F71808FG_REG_WDO_CONF,
386 superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
389 if (wd->pulse_mode) {
391 u8 wdt_conf = superio_inb(wd->sioaddr,
395 wdt_conf = (wdt_conf & 0xfc) | (wd->pulse_val & 0x03);
399 superio_outb(wd->sioaddr, F71808FG_REG_WDT_CONF,
403 superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
408 superio_exit(wd->sioaddr);
415 struct fintek_wdt *wd = watchdog_get_drvdata(wdd);
418 err = superio_enter(wd->sioaddr);
421 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
423 superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
426 superio_exit(wd->sioaddr);
431 static bool fintek_wdt_is_running(struct fintek_wdt *wd, u8 wdt_conf)
433 return (superio_inb(wd->sioaddr, SIO_REG_ENABLE) & BIT(0))
450 struct fintek_wdt *wd;
461 wd = devm_kzalloc(dev, sizeof(*wd), GFP_KERNEL);
462 if (!wd)
467 wd->type = pdata->type;
468 wd->sioaddr = sioaddr;
469 wd->ident.options = WDIOF_SETTIMEOUT
474 snprintf(wd->ident.identity,
475 sizeof(wd->ident.identity), "%s watchdog",
476 fintek_wdt_names[wd->type]);
481 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
492 wdd = &wd->wdd;
494 if (fintek_wdt_is_running(wd, wdt_conf))
500 wdd->info = &wd->ident;
505 watchdog_set_drvdata(wdd, wd);
520 fintek_wdt_set_pulse_width(wd, pulse_width);