Lines Matching defs:dw_wdt
82 struct dw_wdt {
100 #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd)
102 static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt)
104 return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &
108 static void dw_wdt_update_mode(struct dw_wdt *dw_wdt, enum dw_wdt_rmod rmod)
112 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
117 writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
119 dw_wdt->rmod = rmod;
122 static unsigned int dw_wdt_find_best_top(struct dw_wdt *dw_wdt,
133 if (dw_wdt->timeouts[idx].sec >= timeout)
140 *top_val = dw_wdt->timeouts[idx].top_val;
142 return dw_wdt->timeouts[idx].sec;
145 static unsigned int dw_wdt_get_min_timeout(struct dw_wdt *dw_wdt)
154 if (dw_wdt->timeouts[idx].sec)
158 return dw_wdt->timeouts[idx].sec;
161 static unsigned int dw_wdt_get_max_timeout_ms(struct dw_wdt *dw_wdt)
163 struct dw_wdt_timeout *timeout = &dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1];
171 static unsigned int dw_wdt_get_timeout(struct dw_wdt *dw_wdt)
173 int top_val = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
177 if (dw_wdt->timeouts[idx].top_val == top_val)
185 return dw_wdt->timeouts[idx].sec * dw_wdt->rmod;
190 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
192 writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
200 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
212 timeout = dw_wdt_find_best_top(dw_wdt, DIV_ROUND_UP(top_s, dw_wdt->rmod),
214 if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
220 * Set the new value in the watchdog. Some versions of dw_wdt
226 dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
238 wdd->timeout = timeout * dw_wdt->rmod;
247 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
254 dw_wdt_update_mode(dw_wdt, req ? DW_WDT_RMOD_IRQ : DW_WDT_RMOD_RESET);
260 static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)
262 u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
265 if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
271 writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
276 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
279 dw_wdt_ping(&dw_wdt->wdd);
280 dw_wdt_arm_system_reset(dw_wdt);
287 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
289 if (!dw_wdt->rst) {
294 reset_control_assert(dw_wdt->rst);
295 reset_control_deassert(dw_wdt->rst);
303 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
305 writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
306 dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
307 if (dw_wdt_is_enabled(dw_wdt))
309 dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
311 dw_wdt_arm_system_reset(dw_wdt);
321 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
325 val = readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET);
326 sec = val / dw_wdt->rate;
328 if (dw_wdt->rmod == DW_WDT_RMOD_IRQ) {
329 val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
362 struct dw_wdt *dw_wdt = devid;
369 val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
373 watchdog_notify_pretimeout(&dw_wdt->wdd);
380 struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
382 dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
383 dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
385 clk_disable_unprepare(dw_wdt->pclk);
386 clk_disable_unprepare(dw_wdt->clk);
393 struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
394 int err = clk_prepare_enable(dw_wdt->clk);
399 err = clk_prepare_enable(dw_wdt->pclk);
401 clk_disable_unprepare(dw_wdt->clk);
405 writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
406 writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
408 dw_wdt_ping(&dw_wdt->wdd);
423 static void dw_wdt_handle_tops(struct dw_wdt *dw_wdt, const u32 *tops)
437 tout.sec = tops[val] / dw_wdt->rate;
439 do_div(msec, dw_wdt->rate);
447 dst = &dw_wdt->timeouts[tidx];
455 dw_wdt->timeouts[val] = tout;
459 static int dw_wdt_init_timeouts(struct dw_wdt *dw_wdt, struct device *dev)
470 data = readl(dw_wdt->regs + WDOG_COMP_PARAMS_1_REG_OFFSET);
486 dw_wdt_handle_tops(dw_wdt, tops);
487 if (!dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1].sec) {
518 static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt)
520 struct device *dev = dw_wdt->wdd.parent;
529 regset->base = dw_wdt->regs;
531 dw_wdt->dbgfs_dir = debugfs_create_dir(dev_name(dev), NULL);
533 debugfs_create_regset32("registers", 0444, dw_wdt->dbgfs_dir, regset);
536 static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt)
538 debugfs_remove_recursive(dw_wdt->dbgfs_dir);
543 static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt) {}
544 static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt) {}
552 struct dw_wdt *dw_wdt;
555 dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
556 if (!dw_wdt)
559 dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0);
560 if (IS_ERR(dw_wdt->regs))
561 return PTR_ERR(dw_wdt->regs);
569 dw_wdt->clk = devm_clk_get_enabled(dev, "tclk");
570 if (IS_ERR(dw_wdt->clk)) {
571 dw_wdt->clk = devm_clk_get_enabled(dev, NULL);
572 if (IS_ERR(dw_wdt->clk))
573 return PTR_ERR(dw_wdt->clk);
576 dw_wdt->rate = clk_get_rate(dw_wdt->clk);
577 if (dw_wdt->rate == 0)
587 dw_wdt->pclk = devm_clk_get_optional_enabled(dev, "pclk");
588 if (IS_ERR(dw_wdt->pclk))
589 return PTR_ERR(dw_wdt->pclk);
591 dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
592 if (IS_ERR(dw_wdt->rst))
593 return PTR_ERR(dw_wdt->rst);
596 dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
608 pdev->name, dw_wdt);
612 dw_wdt->wdd.info = &dw_wdt_pt_ident;
617 dw_wdt->wdd.info = &dw_wdt_ident;
620 reset_control_deassert(dw_wdt->rst);
622 ret = dw_wdt_init_timeouts(dw_wdt, dev);
626 wdd = &dw_wdt->wdd;
628 wdd->min_timeout = dw_wdt_get_min_timeout(dw_wdt);
629 wdd->max_hw_heartbeat_ms = dw_wdt_get_max_timeout_ms(dw_wdt);
632 watchdog_set_drvdata(wdd, dw_wdt);
641 if (dw_wdt_is_enabled(dw_wdt)) {
642 wdd->timeout = dw_wdt_get_timeout(dw_wdt);
649 platform_set_drvdata(pdev, dw_wdt);
658 dw_wdt_dbgfs_init(dw_wdt);
663 reset_control_assert(dw_wdt->rst);
669 struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
671 dw_wdt_dbgfs_clear(dw_wdt);
673 watchdog_unregister_device(&dw_wdt->wdd);
674 reset_control_assert(dw_wdt->rst);
689 .name = "dw_wdt",