Lines Matching refs:base
45 * <baseaddr> := physical base address
89 void __iomem *base;
114 writel(1, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL);
115 features = readl(vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES);
118 writel(0, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL);
119 features |= readl(vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES);
138 writel(1, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL);
140 vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES);
142 writel(0, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL);
144 vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES);
153 void __iomem *base = vm_dev->base + VIRTIO_MMIO_CONFIG;
163 ptr[i] = readb(base + offset + i);
169 b = readb(base + offset);
173 w = cpu_to_le16(readw(base + offset));
177 l = cpu_to_le32(readl(base + offset));
181 l = cpu_to_le32(readl(base + offset));
183 l = cpu_to_le32(ioread32(base + offset + sizeof l));
195 void __iomem *base = vm_dev->base + VIRTIO_MMIO_CONFIG;
205 writeb(ptr[i], base + offset + i);
213 writeb(b, base + offset);
217 writew(le16_to_cpu(w), base + offset);
221 writel(le32_to_cpu(l), base + offset);
225 writel(le32_to_cpu(l), base + offset);
227 writel(le32_to_cpu(l), base + offset + sizeof l);
241 return readl(vm_dev->base + VIRTIO_MMIO_CONFIG_GENERATION);
248 return readl(vm_dev->base + VIRTIO_MMIO_STATUS) & 0xff;
263 writel(status, vm_dev->base + VIRTIO_MMIO_STATUS);
271 writel(0, vm_dev->base + VIRTIO_MMIO_STATUS);
285 writel(vq->index, vm_dev->base + VIRTIO_MMIO_QUEUE_NOTIFY);
294 writel(data, vm_dev->base + VIRTIO_MMIO_QUEUE_NOTIFY);
309 status = readl(vm_dev->base + VIRTIO_MMIO_INTERRUPT_STATUS);
310 writel(status, vm_dev->base + VIRTIO_MMIO_INTERRUPT_ACK);
341 writel(index, vm_dev->base + VIRTIO_MMIO_QUEUE_SEL);
343 writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN);
345 writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_READY);
346 WARN_ON(readl(vm_dev->base + VIRTIO_MMIO_QUEUE_READY));
393 writel(index, vm_dev->base + VIRTIO_MMIO_QUEUE_SEL);
396 if (readl(vm_dev->base + (vm_dev->version == 1 ?
409 num = readl(vm_dev->base + VIRTIO_MMIO_QUEUE_NUM_MAX);
426 writel(virtqueue_get_vring_size(vq), vm_dev->base + VIRTIO_MMIO_QUEUE_NUM);
443 writel(PAGE_SIZE, vm_dev->base + VIRTIO_MMIO_QUEUE_ALIGN);
444 writel(q_pfn, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN);
449 writel((u32)addr, vm_dev->base + VIRTIO_MMIO_QUEUE_DESC_LOW);
451 vm_dev->base + VIRTIO_MMIO_QUEUE_DESC_HIGH);
454 writel((u32)addr, vm_dev->base + VIRTIO_MMIO_QUEUE_AVAIL_LOW);
456 vm_dev->base + VIRTIO_MMIO_QUEUE_AVAIL_HIGH);
459 writel((u32)addr, vm_dev->base + VIRTIO_MMIO_QUEUE_USED_LOW);
461 vm_dev->base + VIRTIO_MMIO_QUEUE_USED_HIGH);
463 writel(1, vm_dev->base + VIRTIO_MMIO_QUEUE_READY);
479 writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN);
481 writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_READY);
482 WARN_ON(readl(vm_dev->base + VIRTIO_MMIO_QUEUE_READY));
543 writel(id, vm_dev->base + VIRTIO_MMIO_SHM_SEL);
546 len = (u64) readl(vm_dev->base + VIRTIO_MMIO_SHM_LEN_LOW);
547 len |= (u64) readl(vm_dev->base + VIRTIO_MMIO_SHM_LEN_HIGH) << 32;
557 /* Read the region base address */
558 addr = (u64) readl(vm_dev->base + VIRTIO_MMIO_SHM_BASE_LOW);
559 addr |= (u64) readl(vm_dev->base + VIRTIO_MMIO_SHM_BASE_HIGH) << 32;
595 writel(PAGE_SIZE, vm_dev->base + VIRTIO_MMIO_GUEST_PAGE_SIZE);
633 vm_dev->base = devm_platform_ioremap_resource(pdev, 0);
634 if (IS_ERR(vm_dev->base)) {
635 rc = PTR_ERR(vm_dev->base);
640 magic = readl(vm_dev->base + VIRTIO_MMIO_MAGIC_VALUE);
648 vm_dev->version = readl(vm_dev->base + VIRTIO_MMIO_VERSION);
656 vm_dev->vdev.id.device = readl(vm_dev->base + VIRTIO_MMIO_DEVICE_ID);
665 vm_dev->vdev.id.vendor = readl(vm_dev->base + VIRTIO_MMIO_VENDOR_ID);
668 writel(PAGE_SIZE, vm_dev->base + VIRTIO_MMIO_GUEST_PAGE_SIZE);
726 long long base, size;
734 /* Get "@<base>:<irq>[:<id>]" chunks */
736 &base, &irq, &consumed,
748 resources[0].start = base;
749 resources[0].end = base + size - 1;