Lines Matching refs:vgabase
119 svga_tilecursor(par->state.vgabase, info, cursor);
265 regval = vga_r(par->state.vgabase, VGA_MIS_R);
266 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
269 vga_wseq(par->state.vgabase, 0x46, (n | (r << 6)));
270 vga_wseq(par->state.vgabase, 0x47, m);
275 svga_wseq_mask(par->state.vgabase, 0x40, 0x02, 0x02);
276 svga_wseq_mask(par->state.vgabase, 0x40, 0x00, 0x02);
286 void __iomem *vgabase = par->state.vgabase;
289 par->state.vgabase = vgabase;
424 svga_wseq_mask(par->state.vgabase, 0x10, 0x01, 0x01);
425 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
426 svga_wcrt_mask(par->state.vgabase, 0x47, 0x00, 0x01);
429 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
430 svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30);
431 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
434 svga_set_default_gfx_regs(par->state.vgabase);
435 svga_set_default_atc_regs(par->state.vgabase);
436 svga_set_default_seq_regs(par->state.vgabase);
437 svga_set_default_crt_regs(par->state.vgabase);
438 svga_wcrt_multi(par->state.vgabase, vt8623_line_compare_regs, 0xFFFFFFFF);
439 svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, 0);
441 svga_wcrt_multi(par->state.vgabase, vt8623_offset_regs, offset_value);
442 svga_wseq_multi(par->state.vgabase, vt8623_fetch_count_regs, fetch_value);
445 svga_wcrt_mask(par->state.vgabase, 0x03, 0x00, 0x60);
446 svga_wcrt_mask(par->state.vgabase, 0x05, 0x00, 0x60);
449 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
451 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
453 svga_wseq_mask(par->state.vgabase, 0x1E, 0xF0, 0xF0); // DI/DVP bus
454 svga_wseq_mask(par->state.vgabase, 0x2A, 0x0F, 0x0F); // DI/DVP bus
455 svga_wseq_mask(par->state.vgabase, 0x16, 0x08, 0xBF); // FIFO read threshold
456 vga_wseq(par->state.vgabase, 0x17, 0x1F); // FIFO depth
457 vga_wseq(par->state.vgabase, 0x18, 0x4E);
458 svga_wseq_mask(par->state.vgabase, 0x1A, 0x08, 0x08); // enable MMIO ?
460 vga_wcrt(par->state.vgabase, 0x32, 0x00);
461 vga_wcrt(par->state.vgabase, 0x34, 0x00);
462 vga_wcrt(par->state.vgabase, 0x6A, 0x80);
463 vga_wcrt(par->state.vgabase, 0x6A, 0xC0);
465 vga_wgfx(par->state.vgabase, 0x20, 0x00);
466 vga_wgfx(par->state.vgabase, 0x21, 0x00);
467 vga_wgfx(par->state.vgabase, 0x22, 0x00);
474 svga_set_textmode_vga_regs(par->state.vgabase);
475 svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
476 svga_wcrt_mask(par->state.vgabase, 0x11, 0x60, 0x70);
480 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
481 svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE);
482 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70);
486 svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
487 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70);
491 svga_wseq_mask(par->state.vgabase, 0x15, 0x22, 0xFE);
495 svga_wseq_mask(par->state.vgabase, 0x15, 0xB6, 0xFE);
499 svga_wseq_mask(par->state.vgabase, 0x15, 0xAE, 0xFE);
507 svga_set_timings(par->state.vgabase, &vt8623_timing_regs, &(info->var), 1, 1,
516 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
517 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
518 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
586 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
587 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
591 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
592 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
596 svga_wcrt_mask(par->state.vgabase, 0x36, 0x10, 0x30);
597 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
601 svga_wcrt_mask(par->state.vgabase, 0x36, 0x20, 0x30);
602 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
606 svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30);
607 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
632 svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, offset);
732 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
735 memsize1 = (vga_rseq(par->state.vgabase, 0x34) + 1) >> 1;
736 memsize2 = vga_rseq(par->state.vgabase, 0x39) << 2;