Lines Matching defs:par
268 static int vmlfb_get_gpu(struct vml_par *par)
272 par->gpu = pci_get_device(PCI_VENDOR_ID_INTEL, VML_DEVICE_GPU, NULL);
274 if (!par->gpu) {
281 if (pci_enable_device(par->gpu) < 0) {
282 pci_dev_put(par->gpu);
312 static int vmlfb_enable_mmio(struct vml_par *par)
316 par->vdc_mem_base = pci_resource_start(par->vdc, 0);
317 par->vdc_mem_size = pci_resource_len(par->vdc, 0);
318 if (!request_mem_region(par->vdc_mem_base, par->vdc_mem_size, "vmlfb")) {
323 par->vdc_mem = ioremap(par->vdc_mem_base, par->vdc_mem_size);
324 if (par->vdc_mem == NULL) {
331 par->gpu_mem_base = pci_resource_start(par->gpu, 0);
332 par->gpu_mem_size = pci_resource_len(par->gpu, 0);
333 if (!request_mem_region(par->gpu_mem_base, par->gpu_mem_size, "vmlfb")) {
338 par->gpu_mem = ioremap(par->gpu_mem_base, par->gpu_mem_size);
339 if (par->gpu_mem == NULL) {
348 release_mem_region(par->gpu_mem_base, par->gpu_mem_size);
350 iounmap(par->vdc_mem);
352 release_mem_region(par->vdc_mem_base, par->vdc_mem_size);
360 static void vmlfb_disable_mmio(struct vml_par *par)
362 iounmap(par->gpu_mem);
363 release_mem_region(par->gpu_mem_base, par->gpu_mem_size);
364 iounmap(par->vdc_mem);
365 release_mem_region(par->vdc_mem_base, par->vdc_mem_size);
372 static void vmlfb_release_devices(struct vml_par *par)
374 if (atomic_dec_and_test(&par->refcount)) {
375 pci_disable_device(par->gpu);
376 pci_disable_device(par->vdc);
388 struct vml_par *par;
393 par = vinfo->par;
398 vmlfb_disable_mmio(par);
399 vmlfb_release_devices(par);
401 kfree(par);
447 struct vml_par *par;
454 par = kzalloc(sizeof(*par), GFP_KERNEL);
455 if (par == NULL)
464 vinfo->par = par;
465 par->vdc = dev;
466 atomic_set(&par->refcount, 1);
470 if ((err = vmlfb_get_gpu(par)))
482 err = vmlfb_enable_mmio(par);
504 info->par = par;
541 vmlfb_disable_mmio(par);
543 vmlfb_release_devices(par);
547 kfree(par);
705 struct vml_par *par = vinfo->par;
708 VML_WRITE32(par, VML_RCOMPSTAT, 0);
709 while (!(VML_READ32(par, VML_RCOMPSTAT) & VML_MDVO_VDC_I_RCOMP)) ;
712 VML_WRITE32(par, VML_DSPCCNTR,
713 VML_READ32(par, VML_DSPCCNTR) & ~VML_GFX_ENABLE);
714 (void)VML_READ32(par, VML_DSPCCNTR);
719 VML_WRITE32(par, VML_PIPEACONF, 0);
720 (void)VML_READ32(par, VML_PIPEACONF);
728 struct vml_par *par = vinfo->par;
732 (unsigned)VML_READ32(par, VML_HTOTAL_A));
734 (unsigned)VML_READ32(par, VML_HBLANK_A));
736 (unsigned)VML_READ32(par, VML_HSYNC_A));
738 (unsigned)VML_READ32(par, VML_VTOTAL_A));
740 (unsigned)VML_READ32(par, VML_VBLANK_A));
742 (unsigned)VML_READ32(par, VML_VSYNC_A));
744 (unsigned)VML_READ32(par, VML_DSPCSTRIDE));
746 (unsigned)VML_READ32(par, VML_DSPCSIZE));
748 (unsigned)VML_READ32(par, VML_DSPCPOS));
750 (unsigned)VML_READ32(par, VML_DSPARB));
752 (unsigned)VML_READ32(par, VML_DSPCADDR));
754 (unsigned)VML_READ32(par, VML_BCLRPAT_A));
756 (unsigned)VML_READ32(par, VML_CANVSCLR_A));
758 (unsigned)VML_READ32(par, VML_PIPEASRC));
760 (unsigned)VML_READ32(par, VML_PIPEACONF));
762 (unsigned)VML_READ32(par, VML_DSPCCNTR));
764 (unsigned)VML_READ32(par, VML_RCOMPSTAT));
771 struct vml_par *par = vinfo->par;
836 VML_WRITE32(par, VML_HTOTAL_A, ((htotal - 1) << 16) | (hactive - 1));
837 VML_WRITE32(par, VML_HBLANK_A,
839 VML_WRITE32(par, VML_HSYNC_A,
841 VML_WRITE32(par, VML_VTOTAL_A, ((vtotal - 1) << 16) | (vactive - 1));
842 VML_WRITE32(par, VML_VBLANK_A,
844 VML_WRITE32(par, VML_VSYNC_A,
846 VML_WRITE32(par, VML_DSPCSTRIDE, vinfo->stride);
847 VML_WRITE32(par, VML_DSPCSIZE,
849 VML_WRITE32(par, VML_DSPCPOS, 0x00000000);
850 VML_WRITE32(par, VML_DSPARB, VML_FIFO_DEFAULT);
851 VML_WRITE32(par, VML_BCLRPAT_A, 0x00000000);
852 VML_WRITE32(par, VML_CANVSCLR_A, 0x00000000);
853 VML_WRITE32(par, VML_PIPEASRC,
857 VML_WRITE32(par, VML_PIPEACONF, VML_PIPE_ENABLE);
859 VML_WRITE32(par, VML_DSPCCNTR, dspcntr);
861 VML_WRITE32(par, VML_DSPCADDR, (u32) vinfo->vram_start +
865 VML_WRITE32(par, VML_RCOMPSTAT, VML_MDVO_PAD_ENABLE);
867 while (!(VML_READ32(par, VML_RCOMPSTAT) &
893 struct vml_par *par = vinfo->par;
894 u32 cur = VML_READ32(par, VML_PIPEACONF);
901 VML_WRITE32(par, VML_PIPEACONF, cur & ~VML_PIPE_FORCE_BORDER);
902 (void)VML_READ32(par, VML_PIPEACONF);
908 VML_WRITE32(par, VML_PIPEACONF, cur | VML_PIPE_FORCE_BORDER);
909 (void)VML_READ32(par, VML_PIPEACONF);
945 struct vml_par *par = vinfo->par;
948 VML_WRITE32(par, VML_DSPCADDR, (u32) vinfo->vram_start +
951 (void)VML_READ32(par, VML_DSPCADDR);