Lines Matching defs:par
41 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
43 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
45 (struct tridentfb_par *par, const char*,
175 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
177 fb_writel(v, par->io_virt + r);
180 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
182 return fb_readl(par->io_virt + r);
193 struct tridentfb_par *par = data;
194 u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
201 vga_mm_wcrt(par->io_virt, I2C, reg);
206 struct tridentfb_par *par = data;
207 u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
214 vga_mm_wcrt(par->io_virt, I2C, reg);
219 struct tridentfb_par *par = data;
221 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_TGUI);
232 struct tridentfb_par *par = data;
235 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
240 vga_mm_wcrt(par->io_virt, I2C, reg);
245 struct tridentfb_par *par = data;
248 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
253 vga_mm_wcrt(par->io_virt, I2C, reg);
258 struct tridentfb_par *par = data;
260 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SCL_IN);
265 struct tridentfb_par *par = data;
267 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_IN);
272 struct tridentfb_par *par = info->par;
274 strscpy(par->ddc_adapter.name, info->fix.id,
275 sizeof(par->ddc_adapter.name));
276 par->ddc_adapter.owner = THIS_MODULE;
277 par->ddc_adapter.class = I2C_CLASS_DDC;
278 par->ddc_adapter.algo_data = &par->ddc_algo;
279 par->ddc_adapter.dev.parent = info->device;
280 if (is_oldclock(par->chip_id)) { /* not sure if this check is OK */
281 par->ddc_algo.setsda = tridentfb_ddc_setsda_tgui;
282 par->ddc_algo.setscl = tridentfb_ddc_setscl_tgui;
283 par->ddc_algo.getsda = tridentfb_ddc_getsda_tgui;
286 par->ddc_algo.setsda = tridentfb_ddc_setsda;
287 par->ddc_algo.setscl = tridentfb_ddc_setscl;
288 par->ddc_algo.getsda = tridentfb_ddc_getsda;
289 par->ddc_algo.getscl = tridentfb_ddc_getscl;
291 par->ddc_algo.udelay = 10;
292 par->ddc_algo.timeout = 20;
293 par->ddc_algo.data = par;
295 i2c_set_adapdata(&par->ddc_adapter, par);
297 return i2c_bit_add_bus(&par->ddc_adapter);
306 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
312 writemmr(par, 0x21C0, v2);
313 writemmr(par, 0x21C4, v2);
314 writemmr(par, 0x21B8, v2);
315 writemmr(par, 0x21BC, v2);
316 writemmr(par, 0x21D0, v1);
317 writemmr(par, 0x21D4, v1);
318 writemmr(par, 0x21C8, v1);
319 writemmr(par, 0x21CC, v1);
320 writemmr(par, 0x216C, 0);
323 static void blade_wait_engine(struct tridentfb_par *par)
325 while (readmmr(par, STATUS) & 0xFA800000)
329 static void blade_fill_rect(struct tridentfb_par *par,
332 writemmr(par, COLOR, c);
333 writemmr(par, ROP, rop ? ROP_X : ROP_S);
334 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
336 writemmr(par, DST1, point(x, y));
337 writemmr(par, DST2, point(x + w - 1, y + h - 1));
340 static void blade_image_blit(struct tridentfb_par *par, const char *data,
345 writemmr(par, COLOR, c);
346 writemmr(par, BGCOLOR, b);
347 writemmr(par, CMD, 0xa0000000 | 3 << 19);
349 writemmr(par, DST1, point(x, y));
350 writemmr(par, DST2, point(x + w - 1, y + h - 1));
352 iowrite32_rep(par->io_virt + 0x10000, data, size);
355 static void blade_copy_rect(struct tridentfb_par *par,
367 writemmr(par, ROP, ROP_S);
368 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
370 writemmr(par, SRC1, direction ? s2 : s1);
371 writemmr(par, SRC2, direction ? s1 : s2);
372 writemmr(par, DST1, direction ? d2 : d1);
373 writemmr(par, DST2, direction ? d1 : d2);
380 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
401 t_outb(par, x, 0x2125);
403 par->eng_oper = x | 0x40;
405 writemmr(par, 0x2154, v1);
406 writemmr(par, 0x2150, v1);
407 t_outb(par, 3, 0x2126);
410 static void xp_wait_engine(struct tridentfb_par *par)
415 while (t_inb(par, STATUS) & 0x80) {
423 t_outb(par, 0x00, STATUS);
431 static void xp_fill_rect(struct tridentfb_par *par,
434 writemmr(par, 0x2127, ROP_P);
435 writemmr(par, 0x2158, c);
436 writemmr(par, DRAWFL, 0x4000);
437 writemmr(par, OLDDIM, point(h, w));
438 writemmr(par, OLDDST, point(y, x));
439 t_outb(par, 0x01, OLDCMD);
440 t_outb(par, par->eng_oper, 0x2125);
443 static void xp_copy_rect(struct tridentfb_par *par,
467 writemmr(par, DRAWFL, direction);
468 t_outb(par, ROP_S, 0x2127);
469 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
470 writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
471 writemmr(par, OLDDIM, point(h, w));
472 t_outb(par, 0x01, OLDCMD);
478 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
482 writemmr(par, 0x2120, 0xF0000000);
483 writemmr(par, 0x2120, 0x40000000 | tmp);
484 writemmr(par, 0x2120, 0x80000000);
485 writemmr(par, 0x2144, 0x00000000);
486 writemmr(par, 0x2148, 0x00000000);
487 writemmr(par, 0x2150, 0x00000000);
488 writemmr(par, 0x2154, 0x00000000);
489 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
490 writemmr(par, 0x216C, 0x00000000);
491 writemmr(par, 0x2170, 0x00000000);
492 writemmr(par, 0x217C, 0x00000000);
493 writemmr(par, 0x2120, 0x10000000);
494 writemmr(par, 0x2130, (2047 << 16) | 2047);
497 static void image_wait_engine(struct tridentfb_par *par)
499 while (readmmr(par, 0x2164) & 0xF0000000)
503 static void image_fill_rect(struct tridentfb_par *par,
506 writemmr(par, 0x2120, 0x80000000);
507 writemmr(par, 0x2120, 0x90000000 | ROP_S);
509 writemmr(par, 0x2144, c);
511 writemmr(par, DST1, point(x, y));
512 writemmr(par, DST2, point(x + w - 1, y + h - 1));
514 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
517 static void image_copy_rect(struct tridentfb_par *par,
529 writemmr(par, 0x2120, 0x80000000);
530 writemmr(par, 0x2120, 0x90000000 | ROP_S);
532 writemmr(par, SRC1, direction ? s2 : s1);
533 writemmr(par, SRC2, direction ? s1 : s2);
534 writemmr(par, DST1, direction ? d2 : d1);
535 writemmr(par, DST2, direction ? d1 : d2);
536 writemmr(par, 0x2124,
544 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
549 writemmr(par, 0x2148, 0);
550 writemmr(par, 0x214C, point(4095, 2047));
568 fb_writew(x, par->io_virt + 0x2122);
571 static void tgui_fill_rect(struct tridentfb_par *par,
574 t_outb(par, ROP_P, 0x2127);
575 writemmr(par, OLDCLR, c);
576 writemmr(par, DRAWFL, 0x4020);
577 writemmr(par, OLDDIM, point(w - 1, h - 1));
578 writemmr(par, OLDDST, point(x, y));
579 t_outb(par, 1, OLDCMD);
582 static void tgui_copy_rect(struct tridentfb_par *par,
606 writemmr(par, DRAWFL, 0x4 | flags);
607 t_outb(par, ROP_S, 0x2127);
608 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
609 writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
610 writemmr(par, OLDDIM, point(w - 1, h - 1));
611 t_outb(par, 1, OLDCMD);
620 struct tridentfb_par *par = info->par;
634 par->wait_engine(par);
635 par->fill_rect(par, fr->dx, fr->dy, fr->width,
642 struct tridentfb_par *par = info->par;
661 par->wait_engine(par);
662 if (par->image_blit)
663 par->image_blit(par, img->data, img->dx, img->dy,
672 struct tridentfb_par *par = info->par;
678 par->wait_engine(par);
679 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
685 struct tridentfb_par *par = info->par;
688 par->wait_engine(par);
696 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
698 return vga_mm_rcrt(par->io_virt, reg);
701 static inline void write3X4(struct tridentfb_par *par, int reg,
704 vga_mm_wcrt(par->io_virt, reg, val);
707 static inline unsigned char read3CE(struct tridentfb_par *par,
710 return vga_mm_rgfx(par->io_virt, reg);
713 static inline void writeAttr(struct tridentfb_par *par, int reg,
716 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
717 vga_mm_wattr(par->io_virt, reg, val);
720 static inline void write3CE(struct tridentfb_par *par, int reg,
723 vga_mm_wgfx(par->io_virt, reg, val);
726 static void enable_mmio(struct tridentfb_par *par)
733 if (!is_oldprotect(par->chip_id))
741 static void disable_mmio(struct tridentfb_par *par)
744 vga_mm_rseq(par->io_virt, 0x0B);
747 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
748 if (!is_oldprotect(par->chip_id))
749 vga_mm_wseq(par->io_virt, Protection, 0x92);
752 t_outb(par, PCIReg, 0x3D4);
753 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
756 static inline void crtc_unlock(struct tridentfb_par *par)
758 write3X4(par, VGA_CRTC_V_SYNC_END,
759 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
763 static int get_nativex(struct tridentfb_par *par)
770 tmp = (read3CE(par, VertStretch) >> 4) & 3;
793 static inline void set_lwidth(struct tridentfb_par *par, int width)
795 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
798 if (par->chip_id == TGUI9440 || par->chip_id == CYBER9320)
799 write3X4(par, AddColReg,
800 (read3X4(par, AddColReg) & 0xEF) | ((width & 0x100) >> 4));
802 write3X4(par, AddColReg,
803 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
807 static void screen_stretch(struct tridentfb_par *par)
809 if (par->chip_id != CYBERBLADEXPAi1)
810 write3CE(par, BiosReg, 0);
812 write3CE(par, BiosReg, 8);
813 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
814 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
818 static inline void screen_center(struct tridentfb_par *par)
820 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
821 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
825 static void set_screen_start(struct tridentfb_par *par, int base)
828 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
829 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
830 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
831 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
832 tmp = read3X4(par, CRTHiOrd) & 0xF8;
833 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
837 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
843 unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1;
863 if (is_oldclock(par->chip_id)) {
871 if (is3Dchip(par->chip_id)) {
872 vga_mm_wseq(par->io_virt, ClockHigh, hi);
873 vga_mm_wseq(par->io_virt, ClockLow, lo);
875 t_outb(par, lo, 0x43C8);
876 t_outb(par, hi, 0x43C9);
882 static void set_number_of_lines(struct tridentfb_par *par, int lines)
884 int tmp = read3CE(par, CyberEnhance) & 0x8F;
893 write3CE(par, CyberEnhance, tmp);
900 static int is_flatpanel(struct tridentfb_par *par)
904 if (crt || !iscyber(par->chip_id))
906 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
910 static unsigned int get_memsize(struct tridentfb_par *par)
919 switch (par->chip_id) {
924 tmp = read3X4(par, SPR) & 0x0F;
956 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
994 struct tridentfb_par *par = info->par;
1008 if (par->chip_id == TGUI9440 && bpp == 32)
1011 if (par->flatpanel && nativex && var->xres > nativex)
1026 if (!is3Dchip(par->chip_id) &&
1079 if (is_xp(par->chip_id))
1082 switch (par->chip_id) {
1115 struct tridentfb_par *par = info->par;
1121 set_screen_start(par, offset);
1126 static inline void shadowmode_on(struct tridentfb_par *par)
1128 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
1134 struct tridentfb_par *par = info->par;
1167 enable_mmio(par);
1168 crtc_unlock(par);
1169 write3CE(par, CyberControl, 8);
1176 if (par->flatpanel && var->xres < nativex) {
1182 t_outb(par, tmp | 0xC0, VGA_MIS_W);
1184 shadowmode_on(par);
1187 screen_center(par);
1189 screen_stretch(par);
1192 t_outb(par, tmp, VGA_MIS_W);
1193 write3CE(par, CyberControl, 8);
1197 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1198 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1199 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1200 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1201 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1202 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1205 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1206 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1207 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1208 write3X4(par, VGA_CRTC_H_SYNC_END,
1210 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1211 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1223 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1225 tmp = read3X4(par, CRTHiOrd) & 0x07;
1231 write3X4(par, CRTHiOrd, tmp);
1237 write3X4(par, HorizOverflow, tmp);
1242 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1244 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1245 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1246 write3X4(par, VGA_CRTC_MODE, 0xC3);
1248 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1252 write3X4(par, CRTCModuleTest, tmp);
1253 tmp = read3CE(par, MiscIntContReg) & ~0x4;
1256 write3CE(par, MiscIntContReg, tmp);
1259 write3X4(par, GraphEngReg, 0x80);
1276 write3X4(par, PixelBusReg, tmp);
1278 tmp = read3X4(par, DRAMControl);
1279 if (!is_oldprotect(par->chip_id))
1281 if (iscyber(par->chip_id))
1283 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1285 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1286 if (!is_xp(par->chip_id))
1287 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1289 if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
1290 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1292 vga_mm_wseq(par->io_virt, 0, 3);
1293 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1295 vga_mm_wseq(par->io_virt, 2, 0x0F);
1296 vga_mm_wseq(par->io_virt, 3, 0);
1297 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1303 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1304 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1308 set_vclk(par, vclk);
1309 write3CE(par, MiscExtFunc, tmp | 0x12);
1310 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1311 write3CE(par, 0x6, 0x05); /* graphics mode */
1312 write3CE(par, 0x7, 0x0F); /* planes? */
1315 writeAttr(par, 0x10, 0x41);
1316 writeAttr(par, 0x12, 0x0F); /* planes */
1317 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1321 writeAttr(par, tmp, tmp);
1322 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1323 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1338 t_inb(par, VGA_PEL_IW);
1339 t_inb(par, VGA_PEL_MSK);
1340 t_inb(par, VGA_PEL_MSK);
1341 t_inb(par, VGA_PEL_MSK);
1342 t_inb(par, VGA_PEL_MSK);
1343 t_outb(par, tmp, VGA_PEL_MSK);
1344 t_inb(par, VGA_PEL_IW);
1346 if (par->flatpanel)
1347 set_number_of_lines(par, info->var.yres);
1349 set_lwidth(par, info->fix.line_length / 8);
1352 par->init_accel(par, info->var.xres_virtual, bpp);
1366 struct tridentfb_par *par = info->par;
1372 t_outb(par, 0xFF, VGA_PEL_MSK);
1373 t_outb(par, regno, VGA_PEL_IW);
1375 t_outb(par, red >> 10, VGA_PEL_D);
1376 t_outb(par, green >> 10, VGA_PEL_D);
1377 t_outb(par, blue >> 10, VGA_PEL_D);
1402 struct tridentfb_par *par = info->par;
1405 if (par->flatpanel)
1407 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1408 PMCont = t_inb(par, 0x83C6) & 0xFC;
1409 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1435 write3CE(par, PowerStatus, DPMSCont);
1436 t_outb(par, 4, 0x83C8);
1437 t_outb(par, PMCont, 0x83C6);
1480 default_par = info->par;
1580 disable_mmio(info->par);
1713 disable_mmio(info->par);
1724 struct tridentfb_par *par = info->par;
1727 if (par->ddc_registered)
1728 i2c_del_adapter(&par->ddc_adapter);
1729 iounmap(par->io_virt);