Lines Matching refs:TGA_WRITE_REG
282 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
288 TGA_WRITE_REG(par, deep_presets[tga_type] |
296 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
297 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
298 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
304 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
305 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
308 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
309 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
325 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
328 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
330 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
332 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
334 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
350 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
353 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
354 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
355 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
356 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
379 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
385 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
386 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
387 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
393 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
394 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
395 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
396 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
402 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
406 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
409 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
412 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
413 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
414 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
420 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
443 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
455 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
456 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
459 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
462 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
463 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
466 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
467 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
470 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
471 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
474 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
475 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
476 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
477 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
478 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
479 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
506 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
508 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
510 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
511 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
540 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
541 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
542 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
543 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
546 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
547 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
548 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
549 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
556 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
557 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
558 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
559 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
588 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
589 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
592 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
596 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
601 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
602 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
607 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
608 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
613 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
614 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
615 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);