Lines Matching defs:par
174 struct tga_par *par = (struct tga_par *)info->par;
179 if (par->tga_type == TGA_TYPE_8PLANE) {
206 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 8)
244 struct tga_par *par = (struct tga_par *) info->par;
245 int tga_bus_pci = dev_is_pci(par->dev);
246 int tga_bus_tc = TGA_BUS_TC(par->dev);
267 par->htimings = htimings;
268 par->vtimings = vtimings;
270 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
272 /* Store other useful values in par. */
273 par->xres = info->var.xres;
274 par->yres = info->var.yres;
275 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
276 par->bits_per_pixel = info->var.bits_per_pixel;
277 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
279 tga_type = par->tga_type;
282 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
285 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
288 TGA_WRITE_REG(par, deep_presets[tga_type] |
289 (par->sync_on_green ? 0x0 : 0x00010000),
291 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
296 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
297 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
298 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
301 tgafb_set_pll(par, pll_freq);
304 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
305 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
308 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
309 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
315 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
317 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
318 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
319 BT485_WRITE(par, 0x40, BT485_CMD_1);
320 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
321 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
324 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
325 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
328 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
330 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
332 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
334 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
341 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_0, 0x40);
342 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_1, 0x00);
343 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_2,
344 (par->sync_on_green ? 0xc0 : 0x40));
346 BT459_WRITE(par, BT459_REG_ACC, BT459_CUR_CMD_REG, 0x00);
349 BT459_LOAD_ADDR(par, 0x0000);
350 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
353 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
354 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
355 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
356 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
362 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
363 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
364 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
365 (par->sync_on_green ? 0xc0 : 0x40));
367 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
368 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
369 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
370 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
372 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
373 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
374 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
375 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
378 BT463_LOAD_ADDR(par, 0x0000);
379 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
385 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
386 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
387 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
393 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
394 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
395 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
396 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
400 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
402 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
404 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
406 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
408 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
409 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
412 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
413 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
414 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
420 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
437 tgafb_set_pll(struct tga_par *par, int f)
443 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
455 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
456 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
459 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
462 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
463 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
466 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
467 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
470 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
471 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
474 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
475 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
476 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
477 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
478 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
479 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
506 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
508 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
510 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
511 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
528 struct tga_par *par = (struct tga_par *) info->par;
529 int tga_bus_pci = dev_is_pci(par->dev);
530 int tga_bus_tc = TGA_BUS_TC(par->dev);
538 if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
539 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
540 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
541 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
542 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
543 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
544 } else if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
545 BT459_LOAD_ADDR(par, regno);
546 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
547 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
548 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
549 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
555 BT463_LOAD_ADDR(par, regno);
556 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
557 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
558 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
559 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
574 struct tga_par *par = (struct tga_par *) info->par;
580 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
581 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
582 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
587 if (par->vesa_blanked) {
588 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
589 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
590 par->vesa_blanked = 0;
592 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
596 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
601 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
602 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
603 par->vesa_blanked = 1;
607 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
608 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
609 par->vesa_blanked = 1;
613 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
614 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
615 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
616 par->vesa_blanked = 1;
632 struct tga_par *par = (struct tga_par *) info->par;
662 regs_base = par->tga_regs_base;
663 fb_base = par->tga_fb_base;
845 struct tga_par *par = (struct tga_par *) info->par;
868 fb_base = par->tga_fb_base;
931 struct tga_par *par = (struct tga_par *) info->par;
945 regs_base = par->tga_regs_base;
946 fb_base = par->tga_fb_base;
1064 struct tga_par *par = (struct tga_par *) info->par;
1065 void __iomem *tga_regs = par->tga_regs_base;
1109 struct tga_par *par = (struct tga_par *) info->par;
1110 void __iomem *tga_regs = par->tga_regs_base;
1111 void __iomem *tga_fb = par->tga_fb_base;
1159 struct tga_par *par = (struct tga_par *) info->par;
1207 tga_regs = par->tga_regs_base;
1208 tga_fb = par->tga_fb_base;
1322 struct tga_par *par = (struct tga_par *)info->par;
1323 int tga_bus_pci = dev_is_pci(par->dev);
1324 int tga_bus_tc = TGA_BUS_TC(par->dev);
1325 u8 tga_type = par->tga_type;
1365 info->fix.smem_start = (size_t) par->tga_fb_base;
1367 info->fix.mmio_start = (size_t) par->tga_regs_base;
1420 struct tga_par *par;
1430 /* Allocate the fb and par structures. */
1435 par = info->par;
1462 par->dev = dev;
1463 par->tga_mem_base = mem_base;
1464 par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
1465 par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
1466 par->tga_type = tga_type;
1468 par->tga_chip_rev = (to_pci_dev(dev))->revision;
1470 par->tga_chip_rev = TGA_READ_REG(par, TGA_START_REG) & 0xff;
1476 info->screen_base = par->tga_fb_base;
1477 info->pseudo_palette = par->palette;
1517 par->tga_chip_rev);
1525 par->tga_chip_rev);
1548 struct tga_par *par;
1554 par = info->par;
1557 iounmap(par->tga_mem_base);