Lines Matching defs:par
160 static inline u8 vga_inb(struct tdfx_par *par, u32 reg)
162 return inb(par->iobase + reg - 0x300);
165 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val)
167 outb(val, par->iobase + reg - 0x300);
170 static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val)
172 vga_outb(par, GRA_I, idx);
174 vga_outb(par, GRA_D, val);
178 static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val)
180 vga_outb(par, SEQ_I, idx);
182 vga_outb(par, SEQ_D, val);
186 static inline u8 seq_inb(struct tdfx_par *par, u32 idx)
188 vga_outb(par, SEQ_I, idx);
190 return vga_inb(par, SEQ_D);
193 static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val)
195 vga_outb(par, CRT_I, idx);
197 vga_outb(par, CRT_D, val);
201 static inline u8 crt_inb(struct tdfx_par *par, u32 idx)
203 vga_outb(par, CRT_I, idx);
205 return vga_inb(par, CRT_D);
208 static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
210 vga_inb(par, IS1_R);
211 vga_outb(par, ATT_IW, idx);
212 vga_outb(par, ATT_IW, val);
215 static inline void vga_disable_video(struct tdfx_par *par)
219 s = seq_inb(par, 0x01) | 0x20;
220 seq_outb(par, 0x00, 0x01);
221 seq_outb(par, 0x01, s);
222 seq_outb(par, 0x00, 0x03);
225 static inline void vga_enable_video(struct tdfx_par *par)
229 s = seq_inb(par, 0x01) & 0xdf;
230 seq_outb(par, 0x00, 0x01);
231 seq_outb(par, 0x01, s);
232 seq_outb(par, 0x00, 0x03);
235 static inline void vga_enable_palette(struct tdfx_par *par)
237 vga_inb(par, IS1_R);
239 vga_outb(par, ATT_IW, 0x20);
242 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
244 return readl(par->regbase_virt + reg);
247 static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
249 writel(val, par->regbase_virt + reg);
252 static inline void banshee_make_room(struct tdfx_par *par, int size)
256 while ((tdfx_inl(par, STATUS) & 0x1f) < size - 1)
262 struct tdfx_par *par = info->par;
265 banshee_make_room(par, 1);
266 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
269 if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0)
279 static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
281 banshee_make_room(par, 2);
282 tdfx_outl(par, DACADDR, regno);
284 tdfx_inl(par, DACADDR);
285 tdfx_outl(par, DACDATA, c);
339 struct tdfx_par *par = info->par;
344 tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
346 crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
348 banshee_make_room(par, 3);
349 tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
350 tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
352 tdfx_outl(par, PLLCTRL1, reg->mempll);
353 tdfx_outl(par, PLLCTRL2, reg->gfxpll);
355 tdfx_outl(par, PLLCTRL0, reg->vidpll);
357 vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
360 seq_outb(par, i, reg->seq[i]);
363 crt_outb(par, i, reg->crt[i]);
366 gra_outb(par, i, reg->gra[i]);
369 att_outb(par, i, reg->att[i]);
371 crt_outb(par, 0x1a, reg->ext[0]);
372 crt_outb(par, 0x1b, reg->ext[1]);
374 vga_enable_palette(par);
375 vga_enable_video(par);
377 banshee_make_room(par, 9);
378 tdfx_outl(par, VGAINIT0, reg->vgainit0);
379 tdfx_outl(par, DACMODE, reg->dacmode);
380 tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
381 tdfx_outl(par, HWCURPATADDR, reg->curspataddr);
383 tdfx_outl(par, VIDSCREENSIZE, reg->screensize);
384 tdfx_outl(par, VIDDESKSTART, reg->startaddr);
385 tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
386 tdfx_outl(par, VGAINIT1, reg->vgainit1);
387 tdfx_outl(par, MISCINIT0, reg->miscinit0);
389 banshee_make_room(par, 8);
390 tdfx_outl(par, SRCBASE, reg->startaddr);
391 tdfx_outl(par, DSTBASE, reg->startaddr);
392 tdfx_outl(par, COMMANDEXTRA_2D, 0);
393 tdfx_outl(par, CLIP0MIN, 0);
394 tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
395 tdfx_outl(par, CLIP1MIN, 0);
396 tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
397 tdfx_outl(par, SRCXY, 0);
402 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
404 u32 draminit0 = tdfx_inl(par, DRAMINIT0);
405 u32 draminit1 = tdfx_inl(par, DRAMINIT1);
424 miscinit1 = tdfx_inl(par, MISCINIT1);
428 banshee_make_room(par, 1);
429 tdfx_outl(par, MISCINIT1, miscinit1);
437 struct tdfx_par *par = info->par;
465 (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
499 if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
545 struct tdfx_par *par = info->par;
569 if (freq > par->max_pixclock / 2) {
570 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
683 reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
705 reg.miscinit0 = tdfx_inl(par, MISCINIT0);
726 /* Now change fb_fix_screeninfo according to changes in par */
743 struct tdfx_par *par = info->par;
762 do_setpalentry(par, regno, rgbcol);
775 par->palette[regno] = rgbcol;
790 struct tdfx_par *par = info->par;
792 u32 dacmode = tdfx_inl(par, DACMODE);
813 banshee_make_room(par, 1);
814 tdfx_outl(par, DACMODE, dacmode);
816 vga_disable_video(par);
818 vga_enable_video(par);
828 struct tdfx_par *par = info->par;
834 banshee_make_room(par, 1);
835 tdfx_outl(par, VIDDESKSTART, addr);
847 struct tdfx_par *par = info->par;
871 banshee_make_room(par, 6);
872 tdfx_outl(par, DSTFORMAT, fmt);
874 tdfx_outl(par, COLORFORE, rect->color);
876 tdfx_outl(par, COLORFORE, par->palette[rect->color]);
878 tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
879 tdfx_outl(par, DSTBASE, dstbase);
880 tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
881 tdfx_outl(par, LAUNCH_2D, dx | (dy << 16));
890 struct tdfx_par *par = info->par;
933 banshee_make_room(par, 8);
935 tdfx_outl(par, SRCFORMAT, fmt);
936 tdfx_outl(par, DSTFORMAT, fmt);
937 tdfx_outl(par, COMMAND_2D, blitcmd);
938 tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
939 tdfx_outl(par, DSTXY, dx | (dy << 16));
940 tdfx_outl(par, SRCBASE, srcbase);
941 tdfx_outl(par, DSTBASE, dstbase);
942 tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
947 struct tdfx_par *par = info->par;
961 banshee_make_room(par, 6 + ((size + 3) >> 2));
969 banshee_make_room(par, 9);
972 tdfx_outl(par, COLORFORE, image->fg_color);
973 tdfx_outl(par, COLORBACK, image->bg_color);
977 tdfx_outl(par, COLORFORE,
978 par->palette[image->fg_color]);
979 tdfx_outl(par, COLORBACK,
980 par->palette[image->bg_color]);
998 tdfx_outl(par, DSTBASE, dstbase);
999 tdfx_outl(par, SRCXY, 0);
1000 tdfx_outl(par, DSTXY, dx | (dy << 16));
1001 tdfx_outl(par, COMMAND_2D,
1003 tdfx_outl(par, SRCFORMAT, srcfmt);
1004 tdfx_outl(par, DSTFORMAT, dstfmt);
1005 tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
1015 banshee_make_room(par, fifo_free);
1017 tdfx_outl(par, LAUNCH_2D, *(u32 *)chardata);
1022 banshee_make_room(par, 3);
1027 tdfx_outl(par, LAUNCH_2D, *chardata);
1030 tdfx_outl(par, LAUNCH_2D, *(u16 *)chardata);
1033 tdfx_outl(par, LAUNCH_2D,
1042 struct tdfx_par *par = info->par;
1054 vidcfg = tdfx_inl(par, VIDPROCCFG);
1056 tdfx_outl(par, VIDPROCCFG, vidcfg | VIDCFG_HWCURSOR_ENABLE);
1058 tdfx_outl(par, VIDPROCCFG, vidcfg & ~VIDCFG_HWCURSOR_ENABLE);
1081 banshee_make_room(par, 2);
1082 tdfx_outl(par, HWCURC0, bg_color);
1083 tdfx_outl(par, HWCURC1, fg_color);
1092 banshee_make_room(par, 1);
1093 tdfx_outl(par, HWCURLOC, (y << 16) + x);
1170 struct tdfx_par *par = chan->par;
1173 r = tdfx_inl(par, VIDSERPARPORT);
1178 tdfx_outl(par, VIDSERPARPORT, r);
1179 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1185 struct tdfx_par *par = chan->par;
1188 r = tdfx_inl(par, VIDSERPARPORT);
1193 tdfx_outl(par, VIDSERPARPORT, r);
1194 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1204 struct tdfx_par *par = chan->par;
1206 return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SCL_IN));
1212 struct tdfx_par *par = chan->par;
1214 return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SDA_IN));
1220 struct tdfx_par *par = chan->par;
1223 r = tdfx_inl(par, VIDSERPARPORT);
1228 tdfx_outl(par, VIDSERPARPORT, r);
1229 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1235 struct tdfx_par *par = chan->par;
1238 r = tdfx_inl(par, VIDSERPARPORT);
1243 tdfx_outl(par, VIDSERPARPORT, r);
1244 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1250 struct tdfx_par *par = chan->par;
1252 return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SCL_IN));
1258 struct tdfx_par *par = chan->par;
1260 return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SDA_IN));
1287 chan->par = NULL;
1315 chan->par = NULL;
1322 struct tdfx_par *par = info->par;
1324 tdfx_outl(par, VIDINFORMAT, 0x8160);
1325 tdfx_outl(par, VIDSERPARPORT, 0xcffc0020);
1327 par->chan[0].par = par;
1328 par->chan[1].par = par;
1330 tdfxfb_setup_ddc_bus(&par->chan[0], "Voodoo3-DDC", info->device);
1331 tdfxfb_setup_i2c_bus(&par->chan[1], "Voodoo3-I2C", info->device);
1334 static void tdfxfb_delete_i2c_busses(struct tdfx_par *par)
1336 if (par->chan[0].par)
1337 i2c_del_adapter(&par->chan[0].adapter);
1338 par->chan[0].par = NULL;
1340 if (par->chan[1].par)
1341 i2c_del_adapter(&par->chan[1].adapter);
1342 par->chan[1].par = NULL;
1345 static int tdfxfb_probe_i2c_connector(struct tdfx_par *par,
1351 if (par->chan[0].par)
1352 edid = fb_ddc_read(&par->chan[0].adapter);
1395 default_par = info->par;
1610 struct tdfx_par *par = info->par;
1614 tdfxfb_delete_i2c_busses(par);
1616 arch_phys_wc_del(par->wc_cookie);
1617 iounmap(par->regbase_virt);