Lines Matching refs:par
81 static void vgaHWSeqReset(struct savagefb_par *par, int start)
84 VGAwSEQ(0x00, 0x01, par); /* Synchronous Reset */
86 VGAwSEQ(0x00, 0x03, par); /* End Reset */
89 static void vgaHWProtect(struct savagefb_par *par, int on)
97 tmp = VGArSEQ(0x01, par);
99 vgaHWSeqReset(par, 1); /* start synchronous reset */
100 VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */
102 VGAenablePalette(par);
108 tmp = VGArSEQ(0x01, par);
110 VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */
111 vgaHWSeqReset(par, 0); /* clear synchronous reset */
113 VGAdisablePalette(par);
117 static void vgaHWRestore(struct savagefb_par *par, struct savage_reg *reg)
121 VGAwMISC(reg->MiscOutReg, par);
124 VGAwSEQ(i, reg->Sequencer[i], par);
128 VGAwCR(17, reg->CRTC[17] & ~0x80, par);
131 VGAwCR(i, reg->CRTC[i], par);
134 VGAwGR(i, reg->Graphics[i], par);
136 VGAenablePalette(par);
139 VGAwATTR(i, reg->Attribute[i], par);
141 VGAdisablePalette(par);
145 struct savagefb_par *par,
258 savage3D_waitfifo(struct savagefb_par *par, int space)
262 while ((savage_in32(0x48C00, par) & 0x0000ffff) > slots);
266 savage4_waitfifo(struct savagefb_par *par, int space)
270 while ((savage_in32(0x48C60, par) & 0x001fffff) > slots);
274 savage2000_waitfifo(struct savagefb_par *par, int space)
278 while ((savage_in32(0x48C60, par) & 0x0000ffff) > slots);
283 savage3D_waitidle(struct savagefb_par *par)
285 while ((savage_in32(0x48C00, par) & 0x0008ffff) != 0x80000);
289 savage4_waitidle(struct savagefb_par *par)
291 while ((savage_in32(0x48C60, par) & 0x00a00000) != 0x00a00000);
295 savage2000_waitidle(struct savagefb_par *par)
297 while ((savage_in32(0x48C60, par) & 0x009fffff));
302 SavageSetup2DEngine(struct savagefb_par *par)
307 BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth);
308 BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth);
310 switch(par->chip) {
314 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
317 (par->cob_offset >> 11) | (par->cob_index << 29),
318 par);
320 savage_out32(0x48C10, 0x78207220, par);
321 savage_out32(0x48C0C, 0, par);
323 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
331 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
333 savage_out32(0x48C10, 0x00700040, par);
334 savage_out32(0x48C0C, 0, par);
336 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);
340 savage_out32(0x48C18, 0, par);
343 (par->cob_offset >> 7) | (par->cob_index),
344 par);
346 savage_out32(0x48A30, 0, par);
348 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,
349 par);
355 vga_out8(0x3d4, 0x31, par);
356 vga_out8(0x3d5, 0x0c, par);
359 vga_out8(0x3d4, 0x50, par);
360 vga_out8(0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
363 vga_out8(0x3d4, 0x40, par);
364 vga_out8(0x3d5, 0x01, par);
366 savage_out32(MONO_PAT_0, ~0, par);
367 savage_out32(MONO_PAT_1, ~0, par);
370 savage_out32(0x8128, ~0, par); /* enable all write planes */
371 savage_out32(0x812C, ~0, par); /* enable all read planes */
372 savage_out16(0x8134, 0x27, par);
373 savage_out16(0x8136, 0x07, par);
376 par->bci_ptr = 0;
377 par->SavageWaitFifo(par, 4);
389 par->bci_ptr = 0;
390 par->SavageWaitFifo(par, 4);
400 struct savagefb_par *par = info->par;
404 par->bci_ptr = 0;
405 par->SavageWaitFifo(par,3);
411 static void SavageSetup2DEngine(struct savagefb_par *par) {}
508 static void SavagePrintRegs(struct savagefb_par *par)
520 vga_out8(0x3c4, i, par);
521 printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par));
530 vga_out8(vgaCRIndex, i, par);
531 printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par));
540 static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)
544 vga_out16(0x3d4, 0x4838, par);
545 vga_out16(0x3d4, 0xa039, par);
546 vga_out16(0x3c4, 0x0608, par);
548 vga_out8(0x3d4, 0x66, par);
549 cr66 = vga_in8(0x3d5, par);
550 vga_out8(0x3d5, cr66 | 0x80, par);
551 vga_out8(0x3d4, 0x3a, par);
552 cr3a = vga_in8(0x3d5, par);
553 vga_out8(0x3d5, cr3a | 0x80, par);
554 vga_out8(0x3d4, 0x53, par);
555 cr53 = vga_in8(0x3d5, par);
556 vga_out8(0x3d5, cr53 & 0x7f, par);
558 vga_out8(0x3d4, 0x66, par);
559 vga_out8(0x3d5, cr66, par);
560 vga_out8(0x3d4, 0x3a, par);
561 vga_out8(0x3d5, cr3a, par);
563 vga_out8(0x3d4, 0x66, par);
564 vga_out8(0x3d5, cr66, par);
565 vga_out8(0x3d4, 0x3a, par);
566 vga_out8(0x3d5, cr3a, par);
569 vga_out8(0x3c4, 0x08, par);
570 reg->SR08 = vga_in8(0x3c5, par);
571 vga_out8(0x3c5, 0x06, par);
574 vga_out8(0x3d4, 0x31, par);
575 reg->CR31 = vga_in8(0x3d5, par);
576 vga_out8(0x3d4, 0x32, par);
577 reg->CR32 = vga_in8(0x3d5, par);
578 vga_out8(0x3d4, 0x34, par);
579 reg->CR34 = vga_in8(0x3d5, par);
580 vga_out8(0x3d4, 0x36, par);
581 reg->CR36 = vga_in8(0x3d5, par);
582 vga_out8(0x3d4, 0x3a, par);
583 reg->CR3A = vga_in8(0x3d5, par);
584 vga_out8(0x3d4, 0x40, par);
585 reg->CR40 = vga_in8(0x3d5, par);
586 vga_out8(0x3d4, 0x42, par);
587 reg->CR42 = vga_in8(0x3d5, par);
588 vga_out8(0x3d4, 0x45, par);
589 reg->CR45 = vga_in8(0x3d5, par);
590 vga_out8(0x3d4, 0x50, par);
591 reg->CR50 = vga_in8(0x3d5, par);
592 vga_out8(0x3d4, 0x51, par);
593 reg->CR51 = vga_in8(0x3d5, par);
594 vga_out8(0x3d4, 0x53, par);
595 reg->CR53 = vga_in8(0x3d5, par);
596 vga_out8(0x3d4, 0x58, par);
597 reg->CR58 = vga_in8(0x3d5, par);
598 vga_out8(0x3d4, 0x60, par);
599 reg->CR60 = vga_in8(0x3d5, par);
600 vga_out8(0x3d4, 0x66, par);
601 reg->CR66 = vga_in8(0x3d5, par);
602 vga_out8(0x3d4, 0x67, par);
603 reg->CR67 = vga_in8(0x3d5, par);
604 vga_out8(0x3d4, 0x68, par);
605 reg->CR68 = vga_in8(0x3d5, par);
606 vga_out8(0x3d4, 0x69, par);
607 reg->CR69 = vga_in8(0x3d5, par);
608 vga_out8(0x3d4, 0x6f, par);
609 reg->CR6F = vga_in8(0x3d5, par);
611 vga_out8(0x3d4, 0x33, par);
612 reg->CR33 = vga_in8(0x3d5, par);
613 vga_out8(0x3d4, 0x86, par);
614 reg->CR86 = vga_in8(0x3d5, par);
615 vga_out8(0x3d4, 0x88, par);
616 reg->CR88 = vga_in8(0x3d5, par);
617 vga_out8(0x3d4, 0x90, par);
618 reg->CR90 = vga_in8(0x3d5, par);
619 vga_out8(0x3d4, 0x91, par);
620 reg->CR91 = vga_in8(0x3d5, par);
621 vga_out8(0x3d4, 0xb0, par);
622 reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
625 vga_out8(0x3d4, 0x3b, par);
626 reg->CR3B = vga_in8(0x3d5, par);
627 vga_out8(0x3d4, 0x3c, par);
628 reg->CR3C = vga_in8(0x3d5, par);
629 vga_out8(0x3d4, 0x43, par);
630 reg->CR43 = vga_in8(0x3d5, par);
631 vga_out8(0x3d4, 0x5d, par);
632 reg->CR5D = vga_in8(0x3d5, par);
633 vga_out8(0x3d4, 0x5e, par);
634 reg->CR5E = vga_in8(0x3d5, par);
635 vga_out8(0x3d4, 0x65, par);
636 reg->CR65 = vga_in8(0x3d5, par);
639 vga_out8(0x3c4, 0x0e, par);
640 reg->SR0E = vga_in8(0x3c5, par);
641 vga_out8(0x3c4, 0x0f, par);
642 reg->SR0F = vga_in8(0x3c5, par);
643 vga_out8(0x3c4, 0x10, par);
644 reg->SR10 = vga_in8(0x3c5, par);
645 vga_out8(0x3c4, 0x11, par);
646 reg->SR11 = vga_in8(0x3c5, par);
647 vga_out8(0x3c4, 0x12, par);
648 reg->SR12 = vga_in8(0x3c5, par);
649 vga_out8(0x3c4, 0x13, par);
650 reg->SR13 = vga_in8(0x3c5, par);
651 vga_out8(0x3c4, 0x29, par);
652 reg->SR29 = vga_in8(0x3c5, par);
654 vga_out8(0x3c4, 0x15, par);
655 reg->SR15 = vga_in8(0x3c5, par);
656 vga_out8(0x3c4, 0x30, par);
657 reg->SR30 = vga_in8(0x3c5, par);
658 vga_out8(0x3c4, 0x18, par);
659 reg->SR18 = vga_in8(0x3c5, par);
662 if (par->chip == S3_SAVAGE_MX) {
666 vga_out8(0x3c4, 0x54+i, par);
667 reg->SR54[i] = vga_in8(0x3c5, par);
671 vga_out8(0x3d4, 0x66, par);
672 cr66 = vga_in8(0x3d5, par);
673 vga_out8(0x3d5, cr66 | 0x80, par);
674 vga_out8(0x3d4, 0x3a, par);
675 cr3a = vga_in8(0x3d5, par);
676 vga_out8(0x3d5, cr3a | 0x80, par);
679 if (par->chip != S3_SAVAGE_MX) {
680 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
681 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
682 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
683 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
686 vga_out8(0x3d4, 0x3a, par);
687 vga_out8(0x3d5, cr3a, par);
688 vga_out8(0x3d4, 0x66, par);
689 vga_out8(0x3d5, cr66, par);
692 static void savage_set_default_par(struct savagefb_par *par,
697 vga_out16(0x3d4, 0x4838, par);
698 vga_out16(0x3d4, 0xa039, par);
699 vga_out16(0x3c4, 0x0608, par);
701 vga_out8(0x3d4, 0x66, par);
702 cr66 = vga_in8(0x3d5, par);
703 vga_out8(0x3d5, cr66 | 0x80, par);
704 vga_out8(0x3d4, 0x3a, par);
705 cr3a = vga_in8(0x3d5, par);
706 vga_out8(0x3d5, cr3a | 0x80, par);
707 vga_out8(0x3d4, 0x53, par);
708 cr53 = vga_in8(0x3d5, par);
709 vga_out8(0x3d5, cr53 & 0x7f, par);
711 vga_out8(0x3d4, 0x66, par);
712 vga_out8(0x3d5, cr66, par);
713 vga_out8(0x3d4, 0x3a, par);
714 vga_out8(0x3d5, cr3a, par);
716 vga_out8(0x3d4, 0x66, par);
717 vga_out8(0x3d5, cr66, par);
718 vga_out8(0x3d4, 0x3a, par);
719 vga_out8(0x3d5, cr3a, par);
722 vga_out8(0x3c4, 0x08, par);
723 vga_out8(0x3c5, reg->SR08, par);
724 vga_out8(0x3c5, 0x06, par);
727 vga_out8(0x3d4, 0x31, par);
728 vga_out8(0x3d5, reg->CR31, par);
729 vga_out8(0x3d4, 0x32, par);
730 vga_out8(0x3d5, reg->CR32, par);
731 vga_out8(0x3d4, 0x34, par);
732 vga_out8(0x3d5, reg->CR34, par);
733 vga_out8(0x3d4, 0x36, par);
734 vga_out8(0x3d5,reg->CR36, par);
735 vga_out8(0x3d4, 0x3a, par);
736 vga_out8(0x3d5, reg->CR3A, par);
737 vga_out8(0x3d4, 0x40, par);
738 vga_out8(0x3d5, reg->CR40, par);
739 vga_out8(0x3d4, 0x42, par);
740 vga_out8(0x3d5, reg->CR42, par);
741 vga_out8(0x3d4, 0x45, par);
742 vga_out8(0x3d5, reg->CR45, par);
743 vga_out8(0x3d4, 0x50, par);
744 vga_out8(0x3d5, reg->CR50, par);
745 vga_out8(0x3d4, 0x51, par);
746 vga_out8(0x3d5, reg->CR51, par);
747 vga_out8(0x3d4, 0x53, par);
748 vga_out8(0x3d5, reg->CR53, par);
749 vga_out8(0x3d4, 0x58, par);
750 vga_out8(0x3d5, reg->CR58, par);
751 vga_out8(0x3d4, 0x60, par);
752 vga_out8(0x3d5, reg->CR60, par);
753 vga_out8(0x3d4, 0x66, par);
754 vga_out8(0x3d5, reg->CR66, par);
755 vga_out8(0x3d4, 0x67, par);
756 vga_out8(0x3d5, reg->CR67, par);
757 vga_out8(0x3d4, 0x68, par);
758 vga_out8(0x3d5, reg->CR68, par);
759 vga_out8(0x3d4, 0x69, par);
760 vga_out8(0x3d5, reg->CR69, par);
761 vga_out8(0x3d4, 0x6f, par);
762 vga_out8(0x3d5, reg->CR6F, par);
764 vga_out8(0x3d4, 0x33, par);
765 vga_out8(0x3d5, reg->CR33, par);
766 vga_out8(0x3d4, 0x86, par);
767 vga_out8(0x3d5, reg->CR86, par);
768 vga_out8(0x3d4, 0x88, par);
769 vga_out8(0x3d5, reg->CR88, par);
770 vga_out8(0x3d4, 0x90, par);
771 vga_out8(0x3d5, reg->CR90, par);
772 vga_out8(0x3d4, 0x91, par);
773 vga_out8(0x3d5, reg->CR91, par);
774 vga_out8(0x3d4, 0xb0, par);
775 vga_out8(0x3d5, reg->CRB0, par);
778 vga_out8(0x3d4, 0x3b, par);
779 vga_out8(0x3d5, reg->CR3B, par);
780 vga_out8(0x3d4, 0x3c, par);
781 vga_out8(0x3d5, reg->CR3C, par);
782 vga_out8(0x3d4, 0x43, par);
783 vga_out8(0x3d5, reg->CR43, par);
784 vga_out8(0x3d4, 0x5d, par);
785 vga_out8(0x3d5, reg->CR5D, par);
786 vga_out8(0x3d4, 0x5e, par);
787 vga_out8(0x3d5, reg->CR5E, par);
788 vga_out8(0x3d4, 0x65, par);
789 vga_out8(0x3d5, reg->CR65, par);
792 vga_out8(0x3c4, 0x0e, par);
793 vga_out8(0x3c5, reg->SR0E, par);
794 vga_out8(0x3c4, 0x0f, par);
795 vga_out8(0x3c5, reg->SR0F, par);
796 vga_out8(0x3c4, 0x10, par);
797 vga_out8(0x3c5, reg->SR10, par);
798 vga_out8(0x3c4, 0x11, par);
799 vga_out8(0x3c5, reg->SR11, par);
800 vga_out8(0x3c4, 0x12, par);
801 vga_out8(0x3c5, reg->SR12, par);
802 vga_out8(0x3c4, 0x13, par);
803 vga_out8(0x3c5, reg->SR13, par);
804 vga_out8(0x3c4, 0x29, par);
805 vga_out8(0x3c5, reg->SR29, par);
807 vga_out8(0x3c4, 0x15, par);
808 vga_out8(0x3c5, reg->SR15, par);
809 vga_out8(0x3c4, 0x30, par);
810 vga_out8(0x3c5, reg->SR30, par);
811 vga_out8(0x3c4, 0x18, par);
812 vga_out8(0x3c5, reg->SR18, par);
815 if (par->chip == S3_SAVAGE_MX) {
819 vga_out8(0x3c4, 0x54+i, par);
820 vga_out8(0x3c5, reg->SR54[i], par);
824 vga_out8(0x3d4, 0x66, par);
825 cr66 = vga_in8(0x3d5, par);
826 vga_out8(0x3d5, cr66 | 0x80, par);
827 vga_out8(0x3d4, 0x3a, par);
828 cr3a = vga_in8(0x3d5, par);
829 vga_out8(0x3d5, cr3a | 0x80, par);
832 if (par->chip != S3_SAVAGE_MX) {
833 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
834 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
835 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
836 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
839 vga_out8(0x3d4, 0x3a, par);
840 vga_out8(0x3d5, cr3a, par);
841 vga_out8(0x3d4, 0x66, par);
842 vga_out8(0x3d5, cr66, par);
867 struct savagefb_par *par = info->par;
931 if (par->SavagePanelWidth &&
932 (var->xres > par->SavagePanelWidth ||
933 var->yres > par->SavagePanelHeight)) {
936 par->SavagePanelWidth,
937 par->SavagePanelHeight);
973 struct savagefb_par *par,
1002 par->depth = var->bits_per_pixel;
1003 par->vwidth = var->xres_virtual;
1005 if (var->bits_per_pixel == 16 && par->chip == S3_SAVAGE3D) {
1016 vgaHWInit(var, par, &timings, reg);
1025 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))
1031 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1032 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1038 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1039 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1057 vga_out8(0x3d4, 0x3a, par);
1058 tmp = vga_in8(0x3d5, par);
1068 vga_out8(0x3d4, 0x58, par);
1069 reg->CR58 = vga_in8(0x3d5, par) & 0x80;
1076 vga_out8(0x3d4, 0x40, par);
1077 reg->CR40 = vga_in8(0x3d5, par) & ~0x01;
1087 if (par->MCLK <= 0) {
1091 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
1172 if (par->chip == S3_SAVAGE2000)
1181 vga_out8(0x3d4, 0x36, par);
1182 reg->CR36 = vga_in8(0x3d5, par);
1183 vga_out8(0x3d4, 0x68, par);
1184 reg->CR68 = vga_in8(0x3d5, par);
1186 vga_out8(0x3d4, 0x6f, par);
1187 reg->CR6F = vga_in8(0x3d5, par);
1188 vga_out8(0x3d4, 0x86, par);
1189 reg->CR86 = vga_in8(0x3d5, par);
1190 vga_out8(0x3d4, 0x88, par);
1191 reg->CR88 = vga_in8(0x3d5, par) | 0x08;
1192 vga_out8(0x3d4, 0xb0, par);
1193 reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
1210 struct savagefb_par *par = info->par;
1215 par->palette[regno].red = red;
1216 par->palette[regno].green = green;
1217 par->palette[regno].blue = blue;
1218 par->palette[regno].transp = transp;
1222 vga_out8(0x3c8, regno, par);
1224 vga_out8(0x3c9, red >> 10, par);
1225 vga_out8(0x3c9, green >> 10, par);
1226 vga_out8(0x3c9, blue >> 10, par);
1260 static void savagefb_set_par_int(struct savagefb_par *par, struct savage_reg *reg)
1266 par->SavageWaitIdle(par);
1268 vga_out8(0x3c2, 0x23, par);
1270 vga_out16(0x3d4, 0x4838, par);
1271 vga_out16(0x3d4, 0xa539, par);
1272 vga_out16(0x3c4, 0x0608, par);
1274 vgaHWProtect(par, 1);
1283 VerticalRetraceWait(par);
1284 vga_out8(0x3d4, 0x67, par);
1285 cr67 = vga_in8(0x3d5, par);
1286 vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
1288 vga_out8(0x3d4, 0x23, par);
1289 vga_out8(0x3d5, 0x00, par);
1290 vga_out8(0x3d4, 0x26, par);
1291 vga_out8(0x3d5, 0x00, par);
1294 vga_out8(0x3d4, 0x66, par);
1295 vga_out8(0x3d5, reg->CR66, par);
1296 vga_out8(0x3d4, 0x3a, par);
1297 vga_out8(0x3d5, reg->CR3A, par);
1298 vga_out8(0x3d4, 0x31, par);
1299 vga_out8(0x3d5, reg->CR31, par);
1300 vga_out8(0x3d4, 0x32, par);
1301 vga_out8(0x3d5, reg->CR32, par);
1302 vga_out8(0x3d4, 0x58, par);
1303 vga_out8(0x3d5, reg->CR58, par);
1304 vga_out8(0x3d4, 0x53, par);
1305 vga_out8(0x3d5, reg->CR53 & 0x7f, par);
1307 vga_out16(0x3c4, 0x0608, par);
1311 vga_out8(0x3c4, 0x0e, par);
1312 vga_out8(0x3c5, reg->SR0E, par);
1313 vga_out8(0x3c4, 0x0f, par);
1314 vga_out8(0x3c5, reg->SR0F, par);
1315 vga_out8(0x3c4, 0x29, par);
1316 vga_out8(0x3c5, reg->SR29, par);
1317 vga_out8(0x3c4, 0x15, par);
1318 vga_out8(0x3c5, reg->SR15, par);
1321 if (par->chip == S3_SAVAGE_MX) {
1325 vga_out8(0x3c4, 0x54+i, par);
1326 vga_out8(0x3c5, reg->SR54[i], par);
1330 vgaHWRestore (par, reg);
1333 vga_out8(0x3d4, 0x53, par);
1334 vga_out8(0x3d5, reg->CR53, par);
1335 vga_out8(0x3d4, 0x5d, par);
1336 vga_out8(0x3d5, reg->CR5D, par);
1337 vga_out8(0x3d4, 0x5e, par);
1338 vga_out8(0x3d5, reg->CR5E, par);
1339 vga_out8(0x3d4, 0x3b, par);
1340 vga_out8(0x3d5, reg->CR3B, par);
1341 vga_out8(0x3d4, 0x3c, par);
1342 vga_out8(0x3d5, reg->CR3C, par);
1343 vga_out8(0x3d4, 0x43, par);
1344 vga_out8(0x3d5, reg->CR43, par);
1345 vga_out8(0x3d4, 0x65, par);
1346 vga_out8(0x3d5, reg->CR65, par);
1349 vga_out8(0x3d4, 0x67, par);
1351 cr67 = vga_in8(0x3d5, par) & 0xf;
1352 vga_out8(0x3d5, 0x50 | cr67, par);
1354 vga_out8(0x3d4, 0x67, par);
1356 vga_out8(0x3d5, reg->CR67 & ~0x0c, par);
1359 vga_out8(0x3d4, 0x34, par);
1360 vga_out8(0x3d5, reg->CR34, par);
1361 vga_out8(0x3d4, 0x40, par);
1362 vga_out8(0x3d5, reg->CR40, par);
1363 vga_out8(0x3d4, 0x42, par);
1364 vga_out8(0x3d5, reg->CR42, par);
1365 vga_out8(0x3d4, 0x45, par);
1366 vga_out8(0x3d5, reg->CR45, par);
1367 vga_out8(0x3d4, 0x50, par);
1368 vga_out8(0x3d5, reg->CR50, par);
1369 vga_out8(0x3d4, 0x51, par);
1370 vga_out8(0x3d5, reg->CR51, par);
1373 vga_out8(0x3d4, 0x36, par);
1374 vga_out8(0x3d5, reg->CR36, par);
1375 vga_out8(0x3d4, 0x60, par);
1376 vga_out8(0x3d5, reg->CR60, par);
1377 vga_out8(0x3d4, 0x68, par);
1378 vga_out8(0x3d5, reg->CR68, par);
1379 vga_out8(0x3d4, 0x69, par);
1380 vga_out8(0x3d5, reg->CR69, par);
1381 vga_out8(0x3d4, 0x6f, par);
1382 vga_out8(0x3d5, reg->CR6F, par);
1384 vga_out8(0x3d4, 0x33, par);
1385 vga_out8(0x3d5, reg->CR33, par);
1386 vga_out8(0x3d4, 0x86, par);
1387 vga_out8(0x3d5, reg->CR86, par);
1388 vga_out8(0x3d4, 0x88, par);
1389 vga_out8(0x3d5, reg->CR88, par);
1390 vga_out8(0x3d4, 0x90, par);
1391 vga_out8(0x3d5, reg->CR90, par);
1392 vga_out8(0x3d4, 0x91, par);
1393 vga_out8(0x3d5, reg->CR91, par);
1395 if (par->chip == S3_SAVAGE4) {
1396 vga_out8(0x3d4, 0xb0, par);
1397 vga_out8(0x3d5, reg->CRB0, par);
1400 vga_out8(0x3d4, 0x32, par);
1401 vga_out8(0x3d5, reg->CR32, par);
1404 vga_out8(0x3c4, 0x08, par);
1405 vga_out8(0x3c5, 0x06, par);
1411 vga_out8(0x3c4, 0x10, par);
1412 vga_out8(0x3c5, reg->SR10, par);
1413 vga_out8(0x3c4, 0x11, par);
1414 vga_out8(0x3c5, reg->SR11, par);
1418 vga_out8(0x3c4, 0x0e, par);
1419 vga_out8(0x3c5, reg->SR0E, par);
1420 vga_out8(0x3c4, 0x0f, par);
1421 vga_out8(0x3c5, reg->SR0F, par);
1422 vga_out8(0x3c4, 0x12, par);
1423 vga_out8(0x3c5, reg->SR12, par);
1424 vga_out8(0x3c4, 0x13, par);
1425 vga_out8(0x3c5, reg->SR13, par);
1426 vga_out8(0x3c4, 0x29, par);
1427 vga_out8(0x3c5, reg->SR29, par);
1428 vga_out8(0x3c4, 0x18, par);
1429 vga_out8(0x3c5, reg->SR18, par);
1432 vga_out8(0x3c4, 0x15, par);
1433 tmp = vga_in8(0x3c5, par) & ~0x21;
1435 vga_out8(0x3c5, tmp | 0x03, par);
1436 vga_out8(0x3c5, tmp | 0x23, par);
1437 vga_out8(0x3c5, tmp | 0x03, par);
1438 vga_out8(0x3c5, reg->SR15, par);
1441 vga_out8(0x3c4, 0x30, par);
1442 vga_out8(0x3c5, reg->SR30, par);
1443 vga_out8(0x3c4, 0x08, par);
1444 vga_out8(0x3c5, reg->SR08, par);
1447 VerticalRetraceWait(par);
1448 vga_out8(0x3d4, 0x67, par);
1449 vga_out8(0x3d5, reg->CR67, par);
1451 vga_out8(0x3d4, 0x66, par);
1452 cr66 = vga_in8(0x3d5, par);
1453 vga_out8(0x3d5, cr66 | 0x80, par);
1454 vga_out8(0x3d4, 0x3a, par);
1455 cr3a = vga_in8(0x3d5, par);
1456 vga_out8(0x3d5, cr3a | 0x80, par);
1458 if (par->chip != S3_SAVAGE_MX) {
1459 VerticalRetraceWait(par);
1460 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
1461 par->SavageWaitIdle(par);
1462 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
1463 par->SavageWaitIdle(par);
1464 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
1465 par->SavageWaitIdle(par);
1466 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
1469 vga_out8(0x3d4, 0x66, par);
1470 vga_out8(0x3d5, cr66, par);
1471 vga_out8(0x3d4, 0x3a, par);
1472 vga_out8(0x3d5, cr3a, par);
1474 SavageSetup2DEngine(par);
1475 vgaHWProtect(par, 0);
1478 static void savagefb_update_start(struct savagefb_par *par, int base)
1481 vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par);
1482 vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par);
1483 vga_out8(0x3d4, 0x69, par);
1484 vga_out8(0x3d5, (base & 0x7f0000) >> 16, par);
1505 struct savagefb_par *par = info->par;
1510 err = savagefb_decode_var(var, par, &par->state);
1514 if (par->dacSpeedBpp <= 0) {
1516 par->dacSpeedBpp = par->clock[3];
1518 par->dacSpeedBpp = par->clock[2];
1520 par->dacSpeedBpp = par->clock[1];
1522 par->dacSpeedBpp = par->clock[0];
1526 par->maxClock = par->dacSpeedBpp;
1527 par->minClock = 10000;
1529 savagefb_set_par_int(par, &par->state);
1534 SavagePrintRegs(par);
1544 struct savagefb_par *par = info->par;
1550 savagefb_update_start(par, base);
1556 struct savagefb_par *par = info->par;
1559 if (par->display_type == DISP_CRT) {
1560 vga_out8(0x3c4, 0x08, par);
1561 sr8 = vga_in8(0x3c5, par);
1563 vga_out8(0x3c5, sr8, par);
1564 vga_out8(0x3c4, 0x0d, par);
1565 srd = vga_in8(0x3c5, par);
1583 vga_out8(0x3c4, 0x0d, par);
1584 vga_out8(0x3c5, srd, par);
1587 if (par->display_type == DISP_LCD ||
1588 par->display_type == DISP_DFP) {
1592 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1593 vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par);
1598 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1599 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par);
1609 struct savagefb_par *par = info->par;
1611 mutex_lock(&par->open_lock);
1613 if (!par->open_count) {
1614 memset(&par->vgastate, 0, sizeof(par->vgastate));
1615 par->vgastate.flags = VGA_SAVE_CMAP | VGA_SAVE_FONTS |
1617 par->vgastate.vgabase = par->mmio.vbase + 0x8000;
1618 save_vga(&par->vgastate);
1619 savage_get_default_par(par, &par->initial);
1622 par->open_count++;
1623 mutex_unlock(&par->open_lock);
1629 struct savagefb_par *par = info->par;
1631 mutex_lock(&par->open_lock);
1633 if (par->open_count == 1) {
1634 savage_set_default_par(par, &par->initial);
1635 restore_vga(&par->vgastate);
1638 par->open_count--;
1639 mutex_unlock(&par->open_lock);
1684 static void savage_enable_mmio(struct savagefb_par *par)
1690 val = vga_in8(0x3c3, par);
1691 vga_out8(0x3c3, val | 0x01, par);
1692 val = vga_in8(0x3cc, par);
1693 vga_out8(0x3c2, val | 0x01, par);
1695 if (par->chip >= S3_SAVAGE4) {
1696 vga_out8(0x3d4, 0x40, par);
1697 val = vga_in8(0x3d5, par);
1698 vga_out8(0x3d5, val | 1, par);
1703 static void savage_disable_mmio(struct savagefb_par *par)
1709 if (par->chip >= S3_SAVAGE4) {
1710 vga_out8(0x3d4, 0x40, par);
1711 val = vga_in8(0x3d5, par);
1712 vga_out8(0x3d5, val | 1, par);
1719 struct savagefb_par *par = info->par;
1722 if (S3_SAVAGE3D_SERIES(par->chip))
1723 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1726 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1729 par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;
1731 par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len);
1732 if (!par->mmio.vbase) {
1737 par->mmio.vbase);
1739 info->fix.mmio_start = par->mmio.pbase;
1740 info->fix.mmio_len = par->mmio.len;
1742 par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
1743 par->bci_ptr = 0;
1745 savage_enable_mmio(par);
1752 struct savagefb_par *par = info->par;
1755 savage_disable_mmio(par);
1757 if (par->mmio.vbase) {
1758 iounmap(par->mmio.vbase);
1759 par->mmio.vbase = NULL;
1765 struct savagefb_par *par = info->par;
1770 if (S3_SAVAGE3D_SERIES(par->chip))
1775 par->video.pbase = pci_resource_start(par->pcidev, resource);
1776 par->video.len = video_len;
1777 par->video.vbase = ioremap_wc(par->video.pbase, par->video.len);
1779 if (!par->video.vbase) {
1784 "pbase == %x\n", par->video.vbase, par->video.pbase);
1786 info->fix.smem_start = par->video.pbase;
1787 info->fix.smem_len = par->video.len - par->cob_size;
1788 info->screen_base = par->video.vbase;
1789 par->video.wc_cookie = arch_phys_wc_add(par->video.pbase, video_len);
1792 memset_io(par->video.vbase, 0, par->video.len);
1799 struct savagefb_par *par = info->par;
1803 if (par->video.vbase) {
1804 arch_phys_wc_del(par->video.wc_cookie);
1805 iounmap(par->video.vbase);
1806 par->video.vbase = NULL;
1811 static int savage_init_hw(struct savagefb_par *par)
1824 vga_out8(0x3d4, 0x11, par);
1825 tmp = vga_in8(0x3d5, par);
1826 vga_out8(0x3d5, tmp & 0x7f, par);
1829 vga_out16(0x3d4, 0x4838, par);
1830 vga_out16(0x3d4, 0xa039, par);
1831 vga_out16(0x3c4, 0x0608, par);
1833 vga_out8(0x3d4, 0x40, par);
1834 tmp = vga_in8(0x3d5, par);
1835 vga_out8(0x3d5, tmp & ~0x01, par);
1838 vga_out8(0x3d4, 0x38, par);
1839 vga_out8(0x3d5, 0x48, par);
1842 vga_out16(0x3d4, 0x4838, par);
1846 vga_out8(0x3d4, 0x36, par); /* for register CR36 (CONFG_REG1), */
1847 config1 = vga_in8(0x3d5, par); /* get amount of vram installed */
1851 switch (par->chip) {
1863 vga_out8(0x3d4, 0x68, par); /* memory control 1 */
1864 if ((vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6))
1894 vga_out8(0x3d4, 0x66, par);
1895 cr66 = vga_in8(0x3d5, par);
1896 vga_out8(0x3d5, cr66 | 0x02, par);
1899 vga_out8(0x3d4, 0x66, par);
1900 vga_out8(0x3d5, cr66 & ~0x02, par); /* clear reset flag */
1908 vga_out8(0x3d4, 0x3f, par);
1909 cr3f = vga_in8(0x3d5, par);
1910 vga_out8(0x3d5, cr3f | 0x08, par);
1913 vga_out8(0x3d4, 0x3f, par);
1914 vga_out8(0x3d5, cr3f & ~0x08, par); /* clear reset flags */
1918 par->numClocks = 4;
1919 par->clock[0] = 250000;
1920 par->clock[1] = 250000;
1921 par->clock[2] = 220000;
1922 par->clock[3] = 220000;
1925 vga_out8(0x3c4, 0x08, par);
1926 sr8 = vga_in8(0x3c5, par);
1927 vga_out8(0x3c5, 0x06, par);
1928 vga_out8(0x3c4, 0x10, par);
1929 n = vga_in8(0x3c5, par);
1930 vga_out8(0x3c4, 0x11, par);
1931 m = vga_in8(0x3c5, par);
1932 vga_out8(0x3c4, 0x08, par);
1933 vga_out8(0x3c5, sr8, par);
1937 par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
1939 par->MCLK);
1944 if (par->chip == S3_SAVAGE4) {
1947 vga_out8(0x3c4, 0x30, par);
1949 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par);
1950 sr30 = vga_in8(0x3c5, par);
1957 if ((S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1958 S3_MOBILE_TWISTER_SERIES(par->chip)) && !par->crtonly)
1959 par->display_type = DISP_LCD;
1960 else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))
1961 par->display_type = DISP_DFP;
1963 par->display_type = DISP_CRT;
1967 if (par->display_type == DISP_LCD) {
1968 unsigned char cr6b = VGArCR(0x6b, par);
1970 int panelX = (VGArSEQ(0x61, par) +
1971 ((VGArSEQ(0x66, par) & 0x02) << 7) + 1) * 8;
1972 int panelY = (VGArSEQ(0x69, par) +
1973 ((VGArSEQ(0x6e, par) & 0x70) << 4) + 1);
1995 if ((VGArSEQ(0x39, par) & 0x03) == 0) {
1997 } else if ((VGArSEQ(0x30, par) & 0x01) == 0) {
2016 par->SavagePanelWidth = panelX;
2017 par->SavagePanelHeight = panelY;
2020 par->display_type = DISP_CRT;
2023 savage_get_default_par(par, &par->state);
2024 par->save = par->state;
2026 if (S3_SAVAGE4_SERIES(par->chip)) {
2031 par->cob_index = 2;
2032 par->cob_size = 0x8000 << par->cob_index;
2033 par->cob_offset = videoRambytes;
2037 par->cob_index = 7;
2038 par->cob_size = 0x400 << par->cob_index;
2039 par->cob_offset = videoRambytes - par->cob_size;
2048 struct savagefb_par *par = info->par;
2051 par->pcidev = dev;
2061 par->chip = S3_SUPERSAVAGE;
2065 par->chip = S3_SAVAGE4;
2069 par->chip = S3_SAVAGE3D;
2073 par->chip = S3_SAVAGE3D;
2077 par->chip = S3_SAVAGE2000;
2081 par->chip = S3_SAVAGE_MX;
2085 par->chip = S3_SAVAGE_MX;
2089 par->chip = S3_SAVAGE_MX;
2093 par->chip = S3_SAVAGE_MX;
2097 par->chip = S3_PROSAVAGE;
2101 par->chip = S3_PROSAVAGE;
2105 par->chip = S3_TWISTER;
2109 par->chip = S3_TWISTER;
2113 par->chip = S3_PROSAVAGEDDR;
2117 par->chip = S3_PROSAVAGEDDR;
2122 if (S3_SAVAGE3D_SERIES(par->chip)) {
2123 par->SavageWaitIdle = savage3D_waitidle;
2124 par->SavageWaitFifo = savage3D_waitfifo;
2125 } else if (S3_SAVAGE4_SERIES(par->chip) ||
2126 S3_SUPERSAVAGE == par->chip) {
2127 par->SavageWaitIdle = savage4_waitidle;
2128 par->SavageWaitFifo = savage4_waitfifo;
2130 par->SavageWaitIdle = savage2000_waitidle;
2131 par->SavageWaitFifo = savage2000_waitfifo;
2144 info->pseudo_palette = par->pseudo_palette;
2174 struct savagefb_par *par;
2189 par = info->par;
2190 mutex_init(&par->open_lock);
2209 video_len = savage_init_hw(par);
2232 if (par->SavagePanelWidth) {
2236 cvt_mode.xres = par->SavagePanelWidth;
2237 cvt_mode.yres = par->SavagePanelHeight;
2361 struct savagefb_par *par = info->par;
2367 par->pm_state = mesg.event;
2384 savage_set_default_par(par, &par->save);
2385 savage_disable_mmio(par);
2409 struct savagefb_par *par = info->par;
2410 int cur_state = par->pm_state;
2414 par->pm_state = PM_EVENT_ON;
2425 savage_enable_mmio(par);
2426 savage_init_hw(par);