Lines Matching refs:CRTC
126 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
127 CRTC[17] */
128 VGAwCR(17, reg->CRTC[17] & ~0x80, par);
131 VGAwCR(i, reg->CRTC[i], par);
167 * CRTC Controller
169 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5;
170 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
171 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
172 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80;
173 reg->CRTC[0x04] = (timings->HSyncStart >> 3);
174 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
176 reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
177 reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
185 reg->CRTC[0x08] = 0x00;
186 reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
189 reg->CRTC[0x09] |= 0x80;
191 reg->CRTC[0x0a] = 0x00;
192 reg->CRTC[0x0b] = 0x00;
193 reg->CRTC[0x0c] = 0x00;
194 reg->CRTC[0x0d] = 0x00;
195 reg->CRTC[0x0e] = 0x00;
196 reg->CRTC[0x0f] = 0x00;
197 reg->CRTC[0x10] = timings->VSyncStart & 0xff;
198 reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
199 reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
200 reg->CRTC[0x13] = var->xres_virtual >> 4;
201 reg->CRTC[0x14] = 0x00;
202 reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
203 reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
204 reg->CRTC[0x17] = 0xc3;
205 reg->CRTC[0x18] = 0xff;
1123 j = (reg->CRTC[0] + ((i & 0x01) << 8) +
1124 reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
1126 if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) {
1127 if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <=
1128 reg->CRTC[0] + ((i & 0x01) << 8))
1129 j = reg->CRTC[4] + ((i & 0x10) << 4) + 4;
1131 j = reg->CRTC[0] + ((i & 0x01) << 8) + 1;
1136 reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2;
1143 reg->CR91 = reg->CRTC[19] = 0xff & width;
1177 reg->CRTC[0x17] = 0xeb;
1823 /* unprotect CRTC[0-7] */