Lines Matching refs:vgabase
197 return vga_rcrt(par->state.vgabase, DDC_REG);
205 vga_wcrt(par->state.vgabase, DDC_REG, val);
272 /* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */
276 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03);
278 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03);
280 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03);
317 svga_tilecursor(par->state.vgabase, info, cursor);
474 regval = vga_r(par->state.vgabase, VGA_MIS_R);
475 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
484 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
485 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */
487 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5));
488 vga_wseq(par->state.vgabase, 0x13, m - 2);
493 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */
494 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
495 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5));
496 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
508 void __iomem *vgabase = par->state.vgabase;
511 par->state.vgabase = vgabase;
646 vga_wcrt(par->state.vgabase, 0x38, 0x48);
647 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
648 vga_wseq(par->state.vgabase, 0x08, 0x06);
649 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
652 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
653 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
656 svga_set_default_gfx_regs(par->state.vgabase);
657 svga_set_default_atc_regs(par->state.vgabase);
658 svga_set_default_seq_regs(par->state.vgabase);
659 svga_set_default_crt_regs(par->state.vgabase);
660 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);
661 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);
664 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */
665 svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
667 /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */
668 /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */
669 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */
670 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */
672 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
674 /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */
676 /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */
677 /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */
682 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
690 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
691 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */
692 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */
693 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */
696 vga_wcrt(par->state.vgabase, 0x3A, 0x35);
697 svga_wattr(par->state.vgabase, 0x33, 0x00);
700 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
702 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
705 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);
707 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);
710 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);
712 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);
718 vga_wcrt(par->state.vgabase, 0x86, 0x80);
719 vga_wcrt(par->state.vgabase, 0x90, 0x00);
724 vga_wcrt(par->state.vgabase, 0x50, 0x00);
725 vga_wcrt(par->state.vgabase, 0x67, 0x50);
727 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09);
728 vga_wcrt(par->state.vgabase, 0x66, 0x90);
741 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);
742 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
744 vga_wcrt(par->state.vgabase, 0x66, 0x81);
753 vga_wcrt(par->state.vgabase, 0x34, 0x00);
755 vga_wcrt(par->state.vgabase, 0x34, 0x10);
757 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);
765 svga_set_textmode_vga_regs(par->state.vgabase);
768 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
769 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
772 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
776 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
781 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
784 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
785 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
788 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
794 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
795 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
798 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
802 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
810 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
812 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
820 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
822 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
824 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
826 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
829 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
833 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
834 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
848 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
850 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
852 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
854 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
857 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
861 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
862 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
875 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
879 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
880 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
888 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
889 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
893 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,
901 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2);
907 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value);
913 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
914 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
989 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
990 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
994 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
995 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
999 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
1000 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1004 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
1005 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1009 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
1010 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1037 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);
1068 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30);
1069 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e);
1070 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f);
1085 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
1094 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
1103 switch (vga_rcrt(par->state.vgabase, 0x2f)) {
1182 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
1185 cr38 = vga_rcrt(par->state.vgabase, 0x38);
1186 cr39 = vga_rcrt(par->state.vgabase, 0x39);
1187 vga_wseq(par->state.vgabase, 0x08, 0x06);
1188 vga_wcrt(par->state.vgabase, 0x38, 0x48);
1189 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
1193 par->rev = vga_rcrt(par->state.vgabase, 0x2f);
1199 regval = vga_rcrt(par->state.vgabase, 0x36);
1242 regval = vga_rcrt(par->state.vgabase, 0x37);
1256 regval = vga_rseq(par->state.vgabase, 0x10);
1257 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
1261 vga_wcrt(par->state.vgabase, 0x38, cr38);
1262 vga_wcrt(par->state.vgabase, 0x39, cr39);
1279 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */
1357 vga_rcrt(par->state.vgabase, 0x2d),
1358 vga_rcrt(par->state.vgabase, 0x2e),
1359 vga_rcrt(par->state.vgabase, 0x2f),
1360 vga_rcrt(par->state.vgabase, 0x30));