Lines Matching defs:par
192 static u8 s3fb_ddc_read(struct s3fb_info *par)
194 if (s3fb_ddc_needs_mmio(par->chip))
195 return readb(par->mmio + DDC_MMIO_REG);
197 return vga_rcrt(par->state.vgabase, DDC_REG);
200 static void s3fb_ddc_write(struct s3fb_info *par, u8 val)
202 if (s3fb_ddc_needs_mmio(par->chip))
203 writeb(val, par->mmio + DDC_MMIO_REG);
205 vga_wcrt(par->state.vgabase, DDC_REG, val);
210 struct s3fb_info *par = data;
213 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
218 s3fb_ddc_write(par, reg);
223 struct s3fb_info *par = data;
226 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
231 s3fb_ddc_write(par, reg);
236 struct s3fb_info *par = data;
238 return !!(s3fb_ddc_read(par) & DDC_SCL_IN);
243 struct s3fb_info *par = data;
245 return !!(s3fb_ddc_read(par) & DDC_SDA_IN);
250 struct s3fb_info *par = info->par;
252 strscpy(par->ddc_adapter.name, info->fix.id,
253 sizeof(par->ddc_adapter.name));
254 par->ddc_adapter.owner = THIS_MODULE;
255 par->ddc_adapter.class = I2C_CLASS_DDC;
256 par->ddc_adapter.algo_data = &par->ddc_algo;
257 par->ddc_adapter.dev.parent = info->device;
258 par->ddc_algo.setsda = s3fb_ddc_setsda;
259 par->ddc_algo.setscl = s3fb_ddc_setscl;
260 par->ddc_algo.getsda = s3fb_ddc_getsda;
261 par->ddc_algo.getscl = s3fb_ddc_getscl;
262 par->ddc_algo.udelay = 10;
263 par->ddc_algo.timeout = 20;
264 par->ddc_algo.data = par;
266 i2c_set_adapdata(&par->ddc_adapter, par);
272 /* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */
273 if (par->chip == CHIP_357_VIRGE_GX2 ||
274 par->chip == CHIP_359_VIRGE_GX2P ||
275 par->chip == CHIP_260_VIRGE_MX)
276 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03);
278 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03);
280 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03);
282 return i2c_bit_add_bus(&par->ddc_adapter);
315 struct s3fb_info *par = info->par;
317 svga_tilecursor(par->state.vgabase, info, cursor);
461 struct s3fb_info *par = info->par;
466 rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll,
474 regval = vga_r(par->state.vgabase, VGA_MIS_R);
475 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
478 if (par->chip == CHIP_357_VIRGE_GX2 ||
479 par->chip == CHIP_359_VIRGE_GX2P ||
480 par->chip == CHIP_360_TRIO3D_1X ||
481 par->chip == CHIP_362_TRIO3D_2X ||
482 par->chip == CHIP_368_TRIO3D_2X ||
483 par->chip == CHIP_260_VIRGE_MX) {
484 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
485 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */
487 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5));
488 vga_wseq(par->state.vgabase, 0x13, m - 2);
493 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */
494 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
495 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5));
496 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
504 struct s3fb_info *par = info->par;
506 mutex_lock(&(par->open_lock));
507 if (par->ref_count == 0) {
508 void __iomem *vgabase = par->state.vgabase;
510 memset(&(par->state), 0, sizeof(struct vgastate));
511 par->state.vgabase = vgabase;
512 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
513 par->state.num_crtc = 0x70;
514 par->state.num_seq = 0x20;
515 save_vga(&(par->state));
518 par->ref_count++;
519 mutex_unlock(&(par->open_lock));
528 struct s3fb_info *par = info->par;
530 mutex_lock(&(par->open_lock));
531 if (par->ref_count == 0) {
532 mutex_unlock(&(par->open_lock));
536 if (par->ref_count == 1)
537 restore_vga(&(par->state));
539 par->ref_count--;
540 mutex_unlock(&(par->open_lock));
549 struct s3fb_info *par = info->par;
561 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))
604 /* Set video mode from par */
608 struct s3fb_info *par = info->par;
646 vga_wcrt(par->state.vgabase, 0x38, 0x48);
647 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
648 vga_wseq(par->state.vgabase, 0x08, 0x06);
649 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
652 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
653 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
656 svga_set_default_gfx_regs(par->state.vgabase);
657 svga_set_default_atc_regs(par->state.vgabase);
658 svga_set_default_seq_regs(par->state.vgabase);
659 svga_set_default_crt_regs(par->state.vgabase);
660 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);
661 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);
664 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */
665 svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
667 /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */
668 /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */
669 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */
670 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */
672 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
674 /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */
676 /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */
677 /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */
682 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
684 if (par->chip != CHIP_357_VIRGE_GX2 &&
685 par->chip != CHIP_359_VIRGE_GX2P &&
686 par->chip != CHIP_360_TRIO3D_1X &&
687 par->chip != CHIP_362_TRIO3D_2X &&
688 par->chip != CHIP_368_TRIO3D_2X &&
689 par->chip != CHIP_260_VIRGE_MX) {
690 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
691 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */
692 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */
693 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */
696 vga_wcrt(par->state.vgabase, 0x3A, 0x35);
697 svga_wattr(par->state.vgabase, 0x33, 0x00);
700 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
702 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
705 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);
707 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);
710 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);
712 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);
717 if (par->chip == CHIP_375_VIRGE_DX) {
718 vga_wcrt(par->state.vgabase, 0x86, 0x80);
719 vga_wcrt(par->state.vgabase, 0x90, 0x00);
723 if (par->chip == CHIP_988_VIRGE_VX) {
724 vga_wcrt(par->state.vgabase, 0x50, 0x00);
725 vga_wcrt(par->state.vgabase, 0x67, 0x50);
727 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09);
728 vga_wcrt(par->state.vgabase, 0x66, 0x90);
731 if (par->chip == CHIP_357_VIRGE_GX2 ||
732 par->chip == CHIP_359_VIRGE_GX2P ||
733 par->chip == CHIP_360_TRIO3D_1X ||
734 par->chip == CHIP_362_TRIO3D_2X ||
735 par->chip == CHIP_368_TRIO3D_2X ||
736 par->chip == CHIP_365_TRIO3D ||
737 par->chip == CHIP_375_VIRGE_DX ||
738 par->chip == CHIP_385_VIRGE_GX ||
739 par->chip == CHIP_260_VIRGE_MX) {
741 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);
742 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
744 vga_wcrt(par->state.vgabase, 0x66, 0x81);
747 if (par->chip == CHIP_357_VIRGE_GX2 ||
748 par->chip == CHIP_359_VIRGE_GX2P ||
749 par->chip == CHIP_360_TRIO3D_1X ||
750 par->chip == CHIP_362_TRIO3D_2X ||
751 par->chip == CHIP_368_TRIO3D_2X ||
752 par->chip == CHIP_260_VIRGE_MX)
753 vga_wcrt(par->state.vgabase, 0x34, 0x00);
755 vga_wcrt(par->state.vgabase, 0x34, 0x10);
757 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);
765 svga_set_textmode_vga_regs(par->state.vgabase);
768 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
769 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
772 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
776 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
781 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
784 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
785 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
788 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
794 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
795 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
798 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
802 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
804 par->chip == CHIP_357_VIRGE_GX2 ||
805 par->chip == CHIP_359_VIRGE_GX2P ||
806 par->chip == CHIP_360_TRIO3D_1X ||
807 par->chip == CHIP_362_TRIO3D_2X ||
808 par->chip == CHIP_368_TRIO3D_2X ||
809 par->chip == CHIP_260_VIRGE_MX)
810 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
812 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
818 if (par->chip == CHIP_988_VIRGE_VX) {
820 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
822 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
823 } else if (par->chip == CHIP_365_TRIO3D) {
824 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
826 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
829 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
833 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
834 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
835 if (par->chip != CHIP_357_VIRGE_GX2 &&
836 par->chip != CHIP_359_VIRGE_GX2P &&
837 par->chip != CHIP_360_TRIO3D_1X &&
838 par->chip != CHIP_362_TRIO3D_2X &&
839 par->chip != CHIP_368_TRIO3D_2X &&
840 par->chip != CHIP_260_VIRGE_MX)
846 if (par->chip == CHIP_988_VIRGE_VX) {
848 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
850 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
851 } else if (par->chip == CHIP_365_TRIO3D) {
852 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
854 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
857 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
861 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
862 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
863 if (par->chip != CHIP_357_VIRGE_GX2 &&
864 par->chip != CHIP_359_VIRGE_GX2P &&
865 par->chip != CHIP_360_TRIO3D_1X &&
866 par->chip != CHIP_362_TRIO3D_2X &&
867 par->chip != CHIP_368_TRIO3D_2X &&
868 par->chip != CHIP_260_VIRGE_MX)
875 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
879 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
880 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
887 if (par->chip != CHIP_988_VIRGE_VX) {
888 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
889 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
893 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,
901 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2);
907 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value);
913 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
914 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
984 struct s3fb_info *par = info->par;
989 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
990 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
994 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
995 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
999 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
1000 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1004 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
1005 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1009 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
1010 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1022 struct s3fb_info *par = info->par;
1037 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);
1063 static int s3_identification(struct s3fb_info *par)
1065 int chip = par->chip;
1068 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30);
1069 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e);
1070 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f);
1085 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
1094 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
1103 switch (vga_rcrt(par->state.vgabase, 0x2f)) {
1124 struct s3fb_info *par;
1144 par = info->par;
1145 mutex_init(&par->open_lock);
1182 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
1185 cr38 = vga_rcrt(par->state.vgabase, 0x38);
1186 cr39 = vga_rcrt(par->state.vgabase, 0x39);
1187 vga_wseq(par->state.vgabase, 0x08, 0x06);
1188 vga_wcrt(par->state.vgabase, 0x38, 0x48);
1189 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
1192 par->chip = id->driver_data & CHIP_MASK;
1193 par->rev = vga_rcrt(par->state.vgabase, 0x2f);
1194 if (par->chip & CHIP_UNDECIDED_FLAG)
1195 par->chip = s3_identification(par);
1199 regval = vga_rcrt(par->state.vgabase, 0x36);
1200 if (par->chip == CHIP_360_TRIO3D_1X ||
1201 par->chip == CHIP_362_TRIO3D_2X ||
1202 par->chip == CHIP_368_TRIO3D_2X ||
1203 par->chip == CHIP_365_TRIO3D) {
1215 } else if (par->chip == CHIP_357_VIRGE_GX2 ||
1216 par->chip == CHIP_359_VIRGE_GX2P ||
1217 par->chip == CHIP_260_VIRGE_MX) {
1226 } else if (par->chip == CHIP_988_VIRGE_VX) {
1242 regval = vga_rcrt(par->state.vgabase, 0x37);
1256 regval = vga_rseq(par->state.vgabase, 0x10);
1257 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
1258 par->mclk_freq = par->mclk_freq >> (regval >> 5);
1261 vga_wcrt(par->state.vgabase, 0x38, cr38);
1262 vga_wcrt(par->state.vgabase, 0x39, cr39);
1264 strcpy(info->fix.id, s3_names [par->chip]);
1271 info->pseudo_palette = (void*) (par->pseudo_palette);
1276 if (s3fb_ddc_needs_mmio(par->chip)) {
1277 par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE);
1278 if (par->mmio)
1279 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */
1284 if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio)
1286 u8 *edid = fb_ddc_read(&par->ddc_adapter);
1287 par->ddc_registered = true;
1353 info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
1355 if (par->chip == CHIP_UNKNOWN)
1357 vga_rcrt(par->state.vgabase, 0x2d),
1358 vga_rcrt(par->state.vgabase, 0x2e),
1359 vga_rcrt(par->state.vgabase, 0x2f),
1360 vga_rcrt(par->state.vgabase, 0x30));
1366 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
1377 if (par->ddc_registered)
1378 i2c_del_adapter(&par->ddc_adapter);
1379 if (par->mmio)
1380 iounmap(par->mmio);
1398 struct s3fb_info __maybe_unused *par;
1401 par = info->par;
1402 arch_phys_wc_del(par->wc_cookie);
1407 if (par->ddc_registered)
1408 i2c_del_adapter(&par->ddc_adapter);
1409 if (par->mmio)
1410 iounmap(par->mmio);
1426 struct s3fb_info *par = info->par;
1431 mutex_lock(&(par->open_lock));
1433 if (par->ref_count == 0) {
1434 mutex_unlock(&(par->open_lock));
1441 mutex_unlock(&(par->open_lock));
1453 struct s3fb_info *par = info->par;
1458 mutex_lock(&(par->open_lock));
1460 if (par->ref_count == 0) {
1461 mutex_unlock(&(par->open_lock));
1469 mutex_unlock(&(par->open_lock));