Lines Matching refs:chip
62 RIVA_HW_INST *chip
65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01);
70 RIVA_HW_INST *chip
73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
78 RIVA_HW_INST *chip
81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
87 RIVA_HW_INST *chip,
92 VGA_WR08(chip->PCIO, 0x3D4, 0x11);
93 cr11 = VGA_RD08(chip->PCIO, 0x3D5);
96 VGA_WR08(chip->PCIO, 0x3D5, cr11);
100 RIVA_HW_INST *chip,
104 VGA_WR08(chip->PVIO, 0x3C4, 0x06);
105 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
106 vgaLockUnlock(chip, Lock);
110 RIVA_HW_INST *chip,
114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
116 vgaLockUnlock(chip, Lock);
121 RIVA_HW_INST *chip,
126 cursor = chip->CurrentState->cursor1;
127 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) |
129 VGA_WR08(chip->PCIO, 0x3D4, 0x31);
130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);
613 RIVA_HW_INST *chip
620 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
622 MClk = (N * chip->CrystalFreqKHz / M) >> P;
627 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
797 RIVA_HW_INST *chip
804 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
806 MClk = (N * chip->CrystalFreqKHz / M) >> P;
807 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
809 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
810 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);
814 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
1046 RIVA_HW_INST *chip
1053 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
1055 MClk = (N * chip->CrystalFreqKHz / M) >> P;
1056 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
1058 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1059 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);
1063 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ?
1065 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
1091 RIVA_HW_INST *chip,
1110 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
1112 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1157 RIVA_HW_INST *chip
1169 if (chip->CrystalFreqKHz == 13500)
1172 highM = 13 - (chip->Architecture == NV_ARCH_03);
1177 highM = 14 - (chip->Architecture == NV_ARCH_03);
1180 highP = 4 - (chip->Architecture == NV_ARCH_03);
1184 if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))
1188 N = (VClk << P) * M / chip->CrystalFreqKHz;
1190 Freq = (chip->CrystalFreqKHz * N / M) >> P;
1217 RIVA_HW_INST *chip,
1240 if (!CalcVClock(dotClock, &VClk, &m, &n, &p, chip))
1243 switch (chip->Architecture)
1250 chip);
1266 chip);
1278 if((chip->Chipset == NV_CHIP_IGEFORCE2) ||
1279 (chip->Chipset == NV_CHIP_0x01F0))
1285 chip, pdev);
1291 chip);
1293 state->cursor0 = 0x80 | (chip->CursorStart >> 17);
1294 state->cursor1 = (chip->CursorStart >> 11) << 2;
1295 state->cursor2 = chip->CursorStart >> 24;
1297 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0);
1305 if((bpp != 8) && (chip->Architecture != NV_ARCH_03))
1327 NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1])
1330 NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1])
1333 NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1])
1336 NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1])
1339 NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1])
1343 RIVA_HW_INST *chip
1348 switch (chip->Architecture)
1352 chip->Tri03 = NULL;
1353 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);
1363 chip->Tri03 = NULL;
1364 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);
1370 RIVA_HW_INST *chip,
1381 switch (chip->Architecture)
1387 NV_WR32(chip->PFB, 0x00000200, state->config);
1397 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1403 chip->Tri03 = NULL;
1409 chip->Tri03 = NULL;
1413 NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03);
1414 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0);
1415 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1);
1416 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2);
1417 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3);
1418 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0);
1419 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1);
1420 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2);
1421 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3);
1427 NV_WR32(chip->PFB, 0x00000200, state->config);
1436 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1441 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1447 chip->Tri03 = NULL;
1453 chip->Tri03 = NULL;
1456 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
1457 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
1458 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
1459 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
1460 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
1461 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
1462 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
1463 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
1468 if(chip->twoHeads) {
1469 VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1470 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner);
1471 chip->LockUnlock(chip, 0);
1482 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1487 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1493 chip->Tri03 = NULL;
1499 chip->Tri03 = NULL;
1503 if(chip->Architecture == NV_ARCH_10) {
1504 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
1505 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
1506 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
1507 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
1508 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
1509 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
1510 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
1511 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
1512 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3);
1514 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0);
1515 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1);
1516 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2);
1517 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3);
1518 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0);
1519 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1);
1520 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2);
1521 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3);
1522 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3);
1523 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3);
1524 NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200));
1525 NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204));
1527 if(chip->twoHeads) {
1528 NV_WR32(chip->PCRTC0, 0x00000860, state->head);
1529 NV_WR32(chip->PCRTC0, 0x00002860, state->head2);
1531 NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25));
1533 NV_WR32(chip->PMC, 0x00008704, 1);
1534 NV_WR32(chip->PMC, 0x00008140, 0);
1535 NV_WR32(chip->PMC, 0x00008920, 0);
1536 NV_WR32(chip->PMC, 0x00008924, 0);
1537 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff);
1538 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff);
1539 NV_WR32(chip->PMC, 0x00001588, 0);
1541 NV_WR32(chip->PFB, 0x00000240, 0);
1542 NV_WR32(chip->PFB, 0x00000250, 0);
1543 NV_WR32(chip->PFB, 0x00000260, 0);
1544 NV_WR32(chip->PFB, 0x00000270, 0);
1545 NV_WR32(chip->PFB, 0x00000280, 0);
1546 NV_WR32(chip->PFB, 0x00000290, 0);
1547 NV_WR32(chip->PFB, 0x000002A0, 0);
1548 NV_WR32(chip->PFB, 0x000002B0, 0);
1550 NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240));
1551 NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244));
1552 NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248));
1553 NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C));
1554 NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250));
1555 NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254));
1556 NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258));
1557 NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C));
1558 NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260));
1559 NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264));
1560 NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268));
1561 NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C));
1562 NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270));
1563 NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274));
1564 NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278));
1565 NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C));
1566 NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280));
1567 NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284));
1568 NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288));
1569 NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C));
1570 NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290));
1571 NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294));
1572 NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298));
1573 NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C));
1574 NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0));
1575 NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4));
1576 NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8));
1577 NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC));
1578 NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0));
1579 NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4));
1580 NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8));
1581 NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC));
1582 NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000);
1583 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000);
1584 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1585 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008);
1586 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200);
1588 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1589 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1590 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1591 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800);
1593 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1594 NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000);
1595 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004);
1596 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400);
1598 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1599 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800);
1601 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1602 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00);
1604 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1605 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000);
1607 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1608 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400);
1610 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1611 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800);
1613 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1614 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400);
1616 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1617 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000);
1619 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1620 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1622 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1624 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig);
1626 if(chip->flatPanel) {
1627 if((chip->Chipset & 0x0ff0) == 0x0110) {
1628 NV_WR32(chip->PRAMDAC, 0x0528, state->dither);
1630 if((chip->Chipset & 0x0ff0) >= 0x0170) {
1631 NV_WR32(chip->PRAMDAC, 0x083C, state->dither);
1634 VGA_WR08(chip->PCIO, 0x03D4, 0x53);
1635 VGA_WR08(chip->PCIO, 0x03D5, 0);
1636 VGA_WR08(chip->PCIO, 0x03D4, 0x54);
1637 VGA_WR08(chip->PCIO, 0x03D5, 0);
1638 VGA_WR08(chip->PCIO, 0x03D4, 0x21);
1639 VGA_WR08(chip->PCIO, 0x03D5, 0xfa);
1642 VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1643 VGA_WR08(chip->PCIO, 0x03D5, state->extra);
1646 UpdateFifoState(chip);
1650 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1651 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
1652 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1653 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);
1654 VGA_WR08(chip->PCIO, 0x03D4, 0x25);
1655 VGA_WR08(chip->PCIO, 0x03D5, state->screen);
1656 VGA_WR08(chip->PCIO, 0x03D4, 0x28);
1657 VGA_WR08(chip->PCIO, 0x03D5, state->pixel);
1658 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
1659 VGA_WR08(chip->PCIO, 0x03D5, state->horiz);
1660 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
1661 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);
1662 VGA_WR08(chip->PCIO, 0x03D4, 0x20);
1663 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);
1664 VGA_WR08(chip->PCIO, 0x03D4, 0x30);
1665 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
1666 VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1667 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
1668 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1669 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);
1670 VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1671 VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
1673 if(!chip->flatPanel) {
1674 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll);
1675 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel);
1676 if(chip->twoHeads)
1677 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2);
1679 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale);
1681 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general);
1686 NV_WR32(chip->PCRTC, 0x00000140, 0);
1687 NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit);
1691 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01);
1695 chip->CurrentState = state;
1699 chip->FifoFreeCount = 0;
1701 chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0);
1705 RIVA_HW_INST *chip,
1712 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1713 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5);
1714 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1715 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5);
1716 VGA_WR08(chip->PCIO, 0x03D4, 0x25);
1717 state->screen = VGA_RD08(chip->PCIO, 0x03D5);
1718 VGA_WR08(chip->PCIO, 0x03D4, 0x28);
1719 state->pixel = VGA_RD08(chip->PCIO, 0x03D5);
1720 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
1721 state->horiz = VGA_RD08(chip->PCIO, 0x03D5);
1722 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
1723 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);
1724 VGA_WR08(chip->PCIO, 0x03D4, 0x20);
1725 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);
1726 VGA_WR08(chip->PCIO, 0x03D4, 0x30);
1727 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5);
1728 VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1729 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5);
1730 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1731 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5);
1732 VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1733 state->interlace = VGA_RD08(chip->PCIO, 0x03D5);
1734 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508);
1735 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520);
1736 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C);
1737 state->general = NV_RD32(chip->PRAMDAC, 0x00000600);
1738 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848);
1739 state->config = NV_RD32(chip->PFB, 0x00000200);
1740 switch (chip->Architecture)
1743 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630);
1744 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634);
1745 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638);
1746 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C);
1747 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650);
1748 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654);
1749 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658);
1750 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C);
1753 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);
1754 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);
1755 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);
1756 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);
1757 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);
1758 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);
1759 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);
1760 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);
1765 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);
1766 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);
1767 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);
1768 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);
1769 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);
1770 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);
1771 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);
1772 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);
1773 if(chip->twoHeads) {
1774 state->head = NV_RD32(chip->PCRTC0, 0x00000860);
1775 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860);
1776 VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1777 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5);
1779 VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1780 state->extra = VGA_RD08(chip->PCIO, 0x03D5);
1781 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810);
1783 if((chip->Chipset & 0x0ff0) == 0x0110) {
1784 state->dither = NV_RD32(chip->PRAMDAC, 0x0528);
1786 if((chip->Chipset & 0x0ff0) >= 0x0170) {
1787 state->dither = NV_RD32(chip->PRAMDAC, 0x083C);
1794 RIVA_HW_INST *chip,
1798 NV_WR32(chip->PCRTC, 0x800, start);
1803 RIVA_HW_INST *chip,
1814 chip->LockUnlock(chip, 0);
1818 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset);
1820 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset);
1822 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5);
1823 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F));
1824 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5);
1825 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60));
1829 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A);
1830 VGA_WR08(chip->PCIO, 0x3C0, 0x13);
1831 VGA_WR08(chip->PCIO, 0x3C0, pan);
1835 RIVA_HW_INST *chip,
1841 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1843 RIVA_FIFO_FREE(*chip,Tri03,5);
1844 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1846 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1848 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);
1852 RIVA_HW_INST *chip,
1858 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1860 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1862 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1864 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1868 RIVA_HW_INST *chip,
1874 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1876 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1878 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1880 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1884 RIVA_HW_INST *chip,
1890 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1892 RIVA_FIFO_FREE(*chip,Tri03,5);
1893 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);
1895 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);
1897 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);
1901 RIVA_HW_INST *chip,
1907 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1909 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);
1911 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);
1913 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1917 RIVA_HW_INST *chip,
1923 (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]);
1925 RIVA_FIFO_FREE(*chip,Tri03,4);
1926 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007);
1929 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1940 RIVA_HW_INST *chip
1944 * Fill in chip configuration.
1946 if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020)
1948 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
1949 && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02))
1954 chip->RamBandwidthKBytesPerSec = 800000;
1955 switch (NV_RD32(chip->PFB, 0x00000000) & 0x03)
1958 chip->RamAmountKBytes = 1024 * 4;
1961 chip->RamAmountKBytes = 1024 * 2;
1964 chip->RamAmountKBytes = 1024 * 8;
1970 chip->RamBandwidthKBytesPerSec = 1000000;
1971 chip->RamAmountKBytes = 1024 * 8;
1979 chip->RamBandwidthKBytesPerSec = 1000000;
1980 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003)
1983 chip->RamAmountKBytes = 1024 * 8;
1986 chip->RamAmountKBytes = 1024 * 4;
1989 chip->RamAmountKBytes = 1024 * 2;
1993 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500;
1994 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
1995 chip->VBlankBit = 0x00000100;
1996 chip->MaxVClockFreqKHz = 256000;
1998 * Set chip functions.
2000 chip->Busy = nv3Busy;
2001 chip->ShowHideCursor = ShowHideCursor;
2002 chip->LoadStateExt = LoadStateExt;
2003 chip->UnloadStateExt = UnloadStateExt;
2004 chip->SetStartAddress = SetStartAddress3;
2005 chip->SetSurfaces2D = nv3SetSurfaces2D;
2006 chip->SetSurfaces3D = nv3SetSurfaces3D;
2007 chip->LockUnlock = nv3LockUnlock;
2011 RIVA_HW_INST *chip
2015 * Fill in chip configuration.
2017 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100)
2019 chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2
2024 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003)
2027 chip->RamAmountKBytes = 1024 * 32;
2030 chip->RamAmountKBytes = 1024 * 4;
2033 chip->RamAmountKBytes = 1024 * 8;
2037 chip->RamAmountKBytes = 1024 * 16;
2041 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003)
2044 chip->RamBandwidthKBytesPerSec = 800000;
2047 chip->RamBandwidthKBytesPerSec = 1000000;
2050 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500;
2051 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
2052 chip->VBlankBit = 0x00000001;
2053 chip->MaxVClockFreqKHz = 350000;
2055 * Set chip functions.
2057 chip->Busy = nv4Busy;
2058 chip->ShowHideCursor = ShowHideCursor;
2059 chip->LoadStateExt = LoadStateExt;
2060 chip->UnloadStateExt = UnloadStateExt;
2061 chip->SetStartAddress = SetStartAddress;
2062 chip->SetSurfaces2D = nv4SetSurfaces2D;
2063 chip->SetSurfaces3D = nv4SetSurfaces3D;
2064 chip->LockUnlock = nv4LockUnlock;
2068 RIVA_HW_INST *chip,
2079 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001))
2080 NV_WR32(chip->PMC, 0x00000004, 0x01000001);
2084 * Fill in chip configuration.
2090 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
2095 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
2097 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF)
2100 chip->RamAmountKBytes = 1024 * 2;
2103 chip->RamAmountKBytes = 1024 * 4;
2106 chip->RamAmountKBytes = 1024 * 8;
2109 chip->RamAmountKBytes = 1024 * 16;
2112 chip->RamAmountKBytes = 1024 * 32;
2115 chip->RamAmountKBytes = 1024 * 64;
2118 chip->RamAmountKBytes = 1024 * 128;
2121 chip->RamAmountKBytes = 1024 * 16;
2125 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003)
2128 chip->RamBandwidthKBytesPerSec = 800000;
2131 chip->RamBandwidthKBytesPerSec = 1000000;
2134 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ?
2148 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22))
2149 chip->CrystalFreqKHz = 27000;
2155 chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024;
2156 chip->CURSOR = NULL; /* can't set this here */
2157 chip->VBlankBit = 0x00000001;
2158 chip->MaxVClockFreqKHz = 350000;
2160 * Set chip functions.
2162 chip->Busy = nv10Busy;
2163 chip->ShowHideCursor = ShowHideCursor;
2164 chip->LoadStateExt = LoadStateExt;
2165 chip->UnloadStateExt = UnloadStateExt;
2166 chip->SetStartAddress = SetStartAddress;
2167 chip->SetSurfaces2D = nv10SetSurfaces2D;
2168 chip->SetSurfaces3D = nv10SetSurfaces3D;
2169 chip->LockUnlock = nv4LockUnlock;
2183 chip->twoHeads = TRUE;
2186 chip->twoHeads = FALSE;
2192 RIVA_HW_INST *chip,
2200 chip->Version = RIVA_SW_VERSION;
2204 switch (chip->Architecture)
2207 nv3GetConfig(chip);
2210 nv4GetConfig(chip);
2215 nv10GetConfig(chip, pdev, chipset);
2220 chip->Chipset = chipset;
2224 chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]);
2225 chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]);
2226 chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]);
2227 chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]);
2228 chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]);
2229 chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]);
2230 chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]);
2231 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);