Lines Matching defs:par
272 static int riva_bl_get_level_brightness(struct riva_par *par,
275 struct fb_info *info = pci_get_drvdata(par->pdev);
294 struct riva_par *par = bl_get_data(bd);
298 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF;
299 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC;
303 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
305 NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt);
306 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc);
315 static void riva_bl_init(struct riva_par *par)
318 struct fb_info *info = pci_get_drvdata(par->pdev);
322 if (!par->FlatPanel)
336 bd = backlight_device_register(name, info->device, par, &riva_bl_ops,
369 static inline void riva_bl_init(struct riva_par *par) {}
379 static inline void CRTCout(struct riva_par *par, unsigned char index,
382 VGA_WR08(par->riva.PCIO, 0x3d4, index);
383 VGA_WR08(par->riva.PCIO, 0x3d5, val);
386 static inline unsigned char CRTCin(struct riva_par *par,
389 VGA_WR08(par->riva.PCIO, 0x3d4, index);
390 return (VGA_RD08(par->riva.PCIO, 0x3d5));
393 static inline void GRAout(struct riva_par *par, unsigned char index,
396 VGA_WR08(par->riva.PVIO, 0x3ce, index);
397 VGA_WR08(par->riva.PVIO, 0x3cf, val);
400 static inline unsigned char GRAin(struct riva_par *par,
403 VGA_WR08(par->riva.PVIO, 0x3ce, index);
404 return (VGA_RD08(par->riva.PVIO, 0x3cf));
407 static inline void SEQout(struct riva_par *par, unsigned char index,
410 VGA_WR08(par->riva.PVIO, 0x3c4, index);
411 VGA_WR08(par->riva.PVIO, 0x3c5, val);
414 static inline unsigned char SEQin(struct riva_par *par,
417 VGA_WR08(par->riva.PVIO, 0x3c4, index);
418 return (VGA_RD08(par->riva.PVIO, 0x3c5));
421 static inline void ATTRout(struct riva_par *par, unsigned char index,
424 VGA_WR08(par->riva.PCIO, 0x3c0, index);
425 VGA_WR08(par->riva.PCIO, 0x3c0, val);
428 static inline unsigned char ATTRin(struct riva_par *par,
431 VGA_WR08(par->riva.PCIO, 0x3c0, index);
432 return (VGA_RD08(par->riva.PCIO, 0x3c1));
435 static inline void MISCout(struct riva_par *par, unsigned char val)
437 VGA_WR08(par->riva.PVIO, 0x3c2, val);
440 static inline unsigned char MISCin(struct riva_par *par)
442 return (VGA_RD08(par->riva.PVIO, 0x3cc));
463 * @par: pointer to private data
478 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
506 writel(tmp, &par->riva.CURSOR[k++]);
569 * @par: pointer to riva_par object containing info for current riva board
579 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
584 par->riva.LockUnlock(&par->riva, 0);
586 par->riva.UnloadStateExt(&par->riva, ®s->ext);
588 regs->misc_output = MISCin(par);
591 regs->crtc[i] = CRTCin(par, i);
594 regs->attr[i] = ATTRin(par, i);
597 regs->gra[i] = GRAin(par, i);
600 regs->seq[i] = SEQin(par, i);
606 * @par: pointer to riva_par object containing info for current riva board
618 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
624 CRTCout(par, 0x11, 0x00);
626 par->riva.LockUnlock(&par->riva, 0);
628 par->riva.LoadStateExt(&par->riva, state);
630 MISCout(par, regs->misc_output);
638 CRTCout(par, i, regs->crtc[i]);
643 ATTRout(par, i, regs->attr[i]);
646 GRAout(par, i, regs->gra[i]);
649 SEQout(par, i, regs->seq[i]);
669 struct riva_par *par = info->par;
706 if (par->FlatPanel) {
762 if (par->riva.Architecture >= NV_ARCH_10)
763 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
774 rc = CalcStateExt(&par->riva, &newmode.ext, par->pdev, bpp, width,
779 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
781 if (par->FlatPanel == 1) {
785 if (par->SecondCRTC) {
786 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
788 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
793 } else if (par->riva.twoHeads) {
794 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
796 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
799 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
801 if (par->FlatPanel == 1) {
806 par->current_state = newmode;
807 riva_load_state(par, &par->current_state);
808 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
942 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
944 RIVA_FIFO_FREE(par->riva, Patt, 4);
945 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
946 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
947 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
948 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
952 static inline void wait_for_idle(struct riva_par *par)
954 while (par->riva.Busy(&par->riva));
961 riva_set_rop_solid(struct riva_par *par, int rop)
963 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
964 RIVA_FIFO_FREE(par->riva, Rop, 1);
965 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
971 struct riva_par *par = info->par;
973 RIVA_FIFO_FREE(par->riva, Clip, 2);
974 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
975 NV_WR32(&par->riva.Clip->WidthHeight, 0,
978 riva_set_rop_solid(par, 0xcc);
979 wait_for_idle(par);
1024 struct riva_par *par = info->par;
1027 mutex_lock(&par->open_lock);
1028 if (!par->ref_count) {
1030 memset(&par->state, 0, sizeof(struct vgastate));
1031 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1033 if (par->riva.Architecture == NV_ARCH_03)
1034 par->state.flags |= VGA_SAVE_CMAP;
1035 save_vga(&par->state);
1038 CRTCout(par, 0x11, 0xFF);
1039 par->riva.LockUnlock(&par->riva, 0);
1041 riva_save_state(par, &par->initial_state);
1043 par->ref_count++;
1044 mutex_unlock(&par->open_lock);
1051 struct riva_par *par = info->par;
1054 mutex_lock(&par->open_lock);
1055 if (!par->ref_count) {
1056 mutex_unlock(&par->open_lock);
1059 if (par->ref_count == 1) {
1060 par->riva.LockUnlock(&par->riva, 0);
1061 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1062 riva_load_state(par, &par->initial_state);
1064 restore_vga(&par->state);
1066 par->riva.LockUnlock(&par->riva, 1);
1068 par->ref_count--;
1069 mutex_unlock(&par->open_lock);
1077 struct riva_par *par = info->par;
1098 if (par->riva.Architecture == NV_ARCH_03)
1184 struct riva_par *par = info->par;
1189 CRTCout(par, 0x11, 0xFF);
1190 par->riva.LockUnlock(&par->riva, 0);
1197 par->cursor_reset = 1;
1227 struct riva_par *par = info->par;
1232 par->riva.SetStartAddress(&par->riva, base);
1239 struct riva_par *par= info->par;
1242 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1243 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1265 SEQout(par, 0x01, tmp);
1266 CRTCout(par, 0x1a, vesa);
1296 struct riva_par *par = info->par;
1297 RIVA_HW_INST *chip = &par->riva;
1318 if (par->riva.Architecture == NV_ARCH_03) {
1321 par->palette[regno] = ((red & 0xf800) >> 1) |
1326 par->palette[regno] = ((red & 0xff00) << 8) |
1385 struct riva_par *par = info->par;
1396 if (par->riva.Architecture != NV_ARCH_03)
1399 color = par->palette[rect->color];
1412 riva_set_rop_solid(par, rop);
1414 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1415 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1417 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1418 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1421 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1424 riva_set_rop_solid(par, 0xcc);
1441 struct riva_par *par = info->par;
1448 RIVA_FIFO_FREE(par->riva, Blt, 3);
1449 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1451 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1454 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1487 struct riva_par *par = info->par;
1505 if (par->riva.Architecture != NV_ARCH_03) {
1509 fgx = par->palette[image->fg_color];
1510 bgx = par->palette[image->bg_color];
1517 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1518 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1520 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1523 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1524 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1525 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1527 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1529 NV_WR32(&par->riva.Bitmap->PointE, 0,
1532 d = &par->riva.Bitmap->MonochromeData01E;
1537 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1547 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1572 struct riva_par *par = info->par;
1580 par->riva.ShowHideCursor(&par->riva, 0);
1582 if (par->cursor_reset) {
1584 par->cursor_reset = 0;
1588 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1598 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1639 par->riva.LockUnlock(&par->riva, 0);
1641 rivafb_load_cursor_image(par, data, bg, fg,
1649 par->riva.ShowHideCursor(&par->riva, 1);
1656 struct riva_par *par = info->par;
1658 wait_for_idle(par);
1688 struct riva_par *par = info->par;
1698 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1707 info->pseudo_palette = par->pseudo_palette;
1723 struct riva_par *par = info->par;
1742 par->EDID = (unsigned char *)pedid;
1755 struct riva_par *par = info->par;
1760 par->riva.LockUnlock(&par->riva, 0);
1761 riva_create_i2c_busses(par);
1763 if (!par->chan[i].par)
1765 riva_probe_i2c_connector(par, i, &par->EDID);
1766 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1773 return (par->EDID) ? 1 : 0;
1830 struct riva_par *par = info->par;
1832 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1839 par->FlatPanel = 1;
1904 default_par = info->par;
2041 riva_bl_init(info->par);
2055 riva_delete_i2c_busses(info->par);
2077 struct riva_par *par = info->par;
2082 riva_delete_i2c_busses(par);
2083 kfree(par->EDID);
2089 arch_phys_wc_del(par->wc_cookie);
2090 iounmap(par->ctrl_base);
2092 if (par->riva.Architecture == NV_ARCH_03)
2093 iounmap(par->riva.PRAMIN);