Lines Matching defs:par
95 static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off)
97 return fb_readl(par->v_regs + off);
100 static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
102 fb_writel(v, par->v_regs + off);
105 static inline void PM3_WAIT(struct pm3_par *par, u32 n)
107 while (PM3_READ_REG(par, PM3InFIFOSpace) < n)
111 static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v)
113 PM3_WAIT(par, 3);
114 PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff);
115 PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff);
117 PM3_WRITE_REG(par, PM3RD_IndexedData, v);
121 static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno,
124 PM3_WAIT(par, 4);
125 PM3_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno);
127 PM3_WRITE_REG(par, PM3RD_PaletteData, r);
129 PM3_WRITE_REG(par, PM3RD_PaletteData, g);
131 PM3_WRITE_REG(par, PM3RD_PaletteData, b);
135 static void pm3fb_clear_colormap(struct pm3_par *par,
141 pm3fb_set_color(par, i, r, g, b);
200 struct pm3_par *par = info->par;
202 PM3_WAIT(par, 2);
203 PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
204 PM3_WRITE_REG(par, PM3Sync, 0);
207 while ((PM3_READ_REG(par, PM3OutFIFOWords)) == 0)
209 } while ((PM3_READ_REG(par, PM3OutputFifo)) != PM3Sync_Tag);
216 struct pm3_par *par = info->par;
219 PM3_WAIT(par, 50);
220 PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
221 PM3_WRITE_REG(par, PM3StatisticMode, 0x0);
222 PM3_WRITE_REG(par, PM3DeltaMode, 0x0);
223 PM3_WRITE_REG(par, PM3RasterizerMode, 0x0);
224 PM3_WRITE_REG(par, PM3ScissorMode, 0x0);
225 PM3_WRITE_REG(par, PM3LineStippleMode, 0x0);
226 PM3_WRITE_REG(par, PM3AreaStippleMode, 0x0);
227 PM3_WRITE_REG(par, PM3GIDMode, 0x0);
228 PM3_WRITE_REG(par, PM3DepthMode, 0x0);
229 PM3_WRITE_REG(par, PM3StencilMode, 0x0);
230 PM3_WRITE_REG(par, PM3StencilData, 0x0);
231 PM3_WRITE_REG(par, PM3ColorDDAMode, 0x0);
232 PM3_WRITE_REG(par, PM3TextureCoordMode, 0x0);
233 PM3_WRITE_REG(par, PM3TextureIndexMode0, 0x0);
234 PM3_WRITE_REG(par, PM3TextureIndexMode1, 0x0);
235 PM3_WRITE_REG(par, PM3TextureReadMode, 0x0);
236 PM3_WRITE_REG(par, PM3LUTMode, 0x0);
237 PM3_WRITE_REG(par, PM3TextureFilterMode, 0x0);
238 PM3_WRITE_REG(par, PM3TextureCompositeMode, 0x0);
239 PM3_WRITE_REG(par, PM3TextureApplicationMode, 0x0);
240 PM3_WRITE_REG(par, PM3TextureCompositeColorMode1, 0x0);
241 PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode1, 0x0);
242 PM3_WRITE_REG(par, PM3TextureCompositeColorMode0, 0x0);
243 PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode0, 0x0);
244 PM3_WRITE_REG(par, PM3FogMode, 0x0);
245 PM3_WRITE_REG(par, PM3ChromaTestMode, 0x0);
246 PM3_WRITE_REG(par, PM3AlphaTestMode, 0x0);
247 PM3_WRITE_REG(par, PM3AntialiasMode, 0x0);
248 PM3_WRITE_REG(par, PM3YUVMode, 0x0);
249 PM3_WRITE_REG(par, PM3AlphaBlendColorMode, 0x0);
250 PM3_WRITE_REG(par, PM3AlphaBlendAlphaMode, 0x0);
251 PM3_WRITE_REG(par, PM3DitherMode, 0x0);
252 PM3_WRITE_REG(par, PM3LogicalOpMode, 0x0);
253 PM3_WRITE_REG(par, PM3RouterMode, 0x0);
254 PM3_WRITE_REG(par, PM3Window, 0x0);
256 PM3_WRITE_REG(par, PM3Config2D, 0x0);
258 PM3_WRITE_REG(par, PM3SpanColorMask, 0xffffffff);
260 PM3_WRITE_REG(par, PM3XBias, 0x0);
261 PM3_WRITE_REG(par, PM3YBias, 0x0);
262 PM3_WRITE_REG(par, PM3DeltaControl, 0x0);
264 PM3_WRITE_REG(par, PM3BitMaskPattern, 0xffffffff);
266 PM3_WRITE_REG(par, PM3FBDestReadEnables,
270 PM3_WRITE_REG(par, PM3FBDestReadBufferAddr0, 0x0);
271 PM3_WRITE_REG(par, PM3FBDestReadBufferOffset0, 0x0);
272 PM3_WRITE_REG(par, PM3FBDestReadBufferWidth0,
275 PM3_WRITE_REG(par, PM3FBDestReadMode,
278 PM3_WRITE_REG(par, PM3FBSourceReadBufferAddr, 0x0);
279 PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset, 0x0);
280 PM3_WRITE_REG(par, PM3FBSourceReadBufferWidth,
282 PM3_WRITE_REG(par, PM3FBSourceReadMode,
286 PM3_WAIT(par, 2);
292 PM3_WRITE_REG(par, PM3PixelSize,
299 PM3_WRITE_REG(par, PM3PixelSize,
306 PM3_WRITE_REG(par, PM3PixelSize,
314 PM3_WRITE_REG(par, PM3RasterizerMode, rm);
317 PM3_WAIT(par, 20);
318 PM3_WRITE_REG(par, PM3FBSoftwareWriteMask, 0xffffffff);
319 PM3_WRITE_REG(par, PM3FBHardwareWriteMask, 0xffffffff);
320 PM3_WRITE_REG(par, PM3FBWriteMode,
324 PM3_WRITE_REG(par, PM3FBWriteBufferAddr0, 0x0);
325 PM3_WRITE_REG(par, PM3FBWriteBufferOffset0, 0x0);
326 PM3_WRITE_REG(par, PM3FBWriteBufferWidth0,
329 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 0x0);
335 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 4095);
337 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, sofb);
341 PM3_WRITE_REG(par, PM3DitherMode,
345 PM3_WRITE_REG(par, PM3DitherMode,
349 PM3_WRITE_REG(par, PM3DitherMode,
359 PM3_WRITE_REG(par, PM3dXDom, 0x0);
360 PM3_WRITE_REG(par, PM3dXSub, 0x0);
361 PM3_WRITE_REG(par, PM3dY, 1 << 16);
362 PM3_WRITE_REG(par, PM3StartXDom, 0x0);
363 PM3_WRITE_REG(par, PM3StartXSub, 0x0);
364 PM3_WRITE_REG(par, PM3StartY, 0x0);
365 PM3_WRITE_REG(par, PM3Count, 0x0);
368 PM3_WRITE_REG(par, PM3LBDestReadMode, 0x0);
369 PM3_WRITE_REG(par, PM3LBDestReadEnables, 0x0);
370 PM3_WRITE_REG(par, PM3LBSourceReadMode, 0x0);
371 PM3_WRITE_REG(par, PM3LBWriteMode, 0x0);
379 struct pm3_par *par = info->par;
417 PM3_WAIT(par, 4);
419 PM3_WRITE_REG(par, PM3Config2D,
425 PM3_WRITE_REG(par, PM3ForegroundColor, color);
427 PM3_WRITE_REG(par, PM3RectanglePosition,
431 PM3_WRITE_REG(par, PM3Render2D,
443 struct pm3_par *par = info->par;
479 PM3_WAIT(par, 6);
481 PM3_WRITE_REG(par, PM3Config2D,
488 PM3_WRITE_REG(par, PM3ScissorMinXY,
490 PM3_WRITE_REG(par, PM3ScissorMaxXY,
494 PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset,
498 PM3_WRITE_REG(par, PM3RectanglePosition,
502 PM3_WRITE_REG(par, PM3Render2D,
514 struct pm3_par *par = info->par;
532 fgx = par->palette[image->fg_color];
533 bgx = par->palette[image->bg_color];
550 PM3_WAIT(par, 7);
552 PM3_WRITE_REG(par, PM3ForegroundColor, fgx);
553 PM3_WRITE_REG(par, PM3BackgroundColor, bgx);
556 PM3_WRITE_REG(par, PM3Config2D,
563 PM3_WRITE_REG(par, PM3ScissorMinXY,
565 PM3_WRITE_REG(par, PM3ScissorMaxXY,
568 PM3_WRITE_REG(par, PM3RectanglePosition,
571 PM3_WRITE_REG(par, PM3Render2D,
588 PM3_WAIT(par, PM3_FIFO_SIZE);
590 PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
596 PM3_WAIT(par, width + 1);
598 PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
615 struct pm3_par *par = info->par;
631 PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, mode);
645 PM3_WRITE_DAC_REG(par, PM3RD_CursorXLow, x & 0xff);
646 PM3_WRITE_DAC_REG(par, PM3RD_CursorXHigh, (x >> 8) & 0xf);
647 PM3_WRITE_DAC_REG(par, PM3RD_CursorYLow, y & 0xff);
648 PM3_WRITE_DAC_REG(par, PM3RD_CursorYHigh, (y >> 8) & 0xf);
652 PM3_WRITE_DAC_REG(par, PM3RD_CursorHotSpotX,
654 PM3_WRITE_DAC_REG(par, PM3RD_CursorHotSpotY,
664 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(39),
666 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(40),
668 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(41),
671 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(42),
673 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(43),
675 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(44),
695 PM3_WRITE_DAC_REG(par, pos++,
699 PM3_WRITE_DAC_REG(par, pos++,
706 PM3_WRITE_DAC_REG(par, pos++, 0);
707 PM3_WRITE_DAC_REG(par, pos++, 0);
711 PM3_WRITE_DAC_REG(par, pos++, 0);
719 struct pm3_par *par = info->par;
734 PM3_WAIT(par, 20);
735 PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff);
736 PM3_WRITE_REG(par, PM3Aperture0, 0x00000000);
737 PM3_WRITE_REG(par, PM3Aperture1, 0x00000000);
738 PM3_WRITE_REG(par, PM3FIFODis, 0x00000007);
740 PM3_WRITE_REG(par, PM3HTotal,
742 PM3_WRITE_REG(par, PM3HsEnd,
744 PM3_WRITE_REG(par, PM3HsStart,
746 PM3_WRITE_REG(par, PM3HbEnd,
748 PM3_WRITE_REG(par, PM3HgEnd,
750 PM3_WRITE_REG(par, PM3ScreenStride,
752 PM3_WRITE_REG(par, PM3VTotal, vtotal - 1);
753 PM3_WRITE_REG(par, PM3VsEnd, vsend - 1);
754 PM3_WRITE_REG(par, PM3VsStart, vsstart - 1);
755 PM3_WRITE_REG(par, PM3VbEnd, vbend);
759 PM3_WRITE_REG(par, PM3ByAperture1Mode,
761 PM3_WRITE_REG(par, PM3ByAperture2Mode,
767 PM3_WRITE_REG(par, PM3ByAperture1Mode,
769 PM3_WRITE_REG(par, PM3ByAperture2Mode,
772 PM3_WRITE_REG(par, PM3ByAperture1Mode,
775 PM3_WRITE_REG(par, PM3ByAperture2Mode,
783 PM3_WRITE_REG(par, PM3ByAperture1Mode,
785 PM3_WRITE_REG(par, PM3ByAperture2Mode,
788 PM3_WRITE_REG(par, PM3ByAperture1Mode,
791 PM3_WRITE_REG(par, PM3ByAperture2Mode,
809 unsigned int video = par->video;
815 PM3_WRITE_REG(par, PM3VideoControl, video);
817 PM3_WRITE_REG(par, PM3VClkCtl,
818 (PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC));
819 PM3_WRITE_REG(par, PM3ScreenBase, par->base);
820 PM3_WRITE_REG(par, PM3ChipConfig,
821 (PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD));
835 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PreScale, m);
836 PM3_WRITE_DAC_REG(par, PM3RD_DClk0FeedbackScale, n);
837 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PostScale, p);
840 PM3_WRITE_DAC_REG(par, PM3RD_IndexControl, 0x00);
843 PM3_SLOW_WRITE_REG(par, PM3RD_IndexControl, 0x00);
845 if ((par->video & PM3VideoControl_HSYNC_MASK) ==
848 if ((par->video & PM3VideoControl_VSYNC_MASK) ==
852 PM3_WRITE_DAC_REG(par, PM3RD_SyncControl, tempsync);
855 PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00);
859 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
861 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
867 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
869 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
877 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
879 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
887 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
889 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
897 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
899 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
906 PM3_WRITE_DAC_REG(par, PM3RD_MiscControl, tempmisc);
1016 struct pm3_par *par = info->par;
1020 par->base = pm3fb_shift_bpp(bpp, (info->var.yoffset * xres)
1022 par->video = 0;
1025 par->video |= PM3VideoControl_HSYNC_ACTIVE_HIGH;
1027 par->video |= PM3VideoControl_HSYNC_ACTIVE_LOW;
1030 par->video |= PM3VideoControl_VSYNC_ACTIVE_HIGH;
1032 par->video |= PM3VideoControl_VSYNC_ACTIVE_LOW;
1035 par->video |= PM3VideoControl_LINE_DOUBLE_ON;
1038 par->video |= PM3VideoControl_ENABLE;
1044 par->video |= PM3VideoControl_PIXELSIZE_8BIT;
1047 par->video |= PM3VideoControl_PIXELSIZE_16BIT;
1050 par->video |= PM3VideoControl_PIXELSIZE_32BIT;
1062 pm3fb_clear_colormap(par, 0, 0, 0);
1063 PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, 0);
1073 struct pm3_par *par = info->par;
1135 pm3fb_set_color(par, regno, red, green, blue);
1143 struct pm3_par *par = info->par;
1146 par->base = pm3fb_shift_bpp(info->var.bits_per_pixel,
1149 PM3_WAIT(par, 1);
1150 PM3_WRITE_REG(par, PM3ScreenBase, par->base);
1156 struct pm3_par *par = info->par;
1157 u32 video = par->video;
1195 PM3_WAIT(par, 1);
1196 PM3_WRITE_REG(par, PM3VideoControl, video);
1226 static unsigned long pm3fb_size_memory(struct pm3_par *par)
1250 tempBypass = PM3_READ_REG(par, PM3MemBypassWriteMask);
1254 PM3_WAIT(par, 1);
1255 PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF);
1299 PM3_WAIT(par, 1);
1300 PM3_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass);
1314 struct pm3_par *par;
1329 * Dynamically allocate info and par
1335 par = info->par;
1354 par->v_regs =
1356 if (!par->v_regs) {
1365 pm3fb_fix.smem_len = pm3fb_size_memory(par);
1385 par->wc_cookie = arch_phys_wc_add(pm3fb_fix.smem_start,
1389 par->video = PM3_READ_REG(par, PM3VideoControl);
1392 info->pseudo_palette = par->palette;
1454 iounmap(par->v_regs);
1470 struct pm3_par *par = info->par;
1475 arch_phys_wc_del(par->wc_cookie);
1478 iounmap(par->v_regs);