Lines Matching defs:par
111 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
137 NV_WR32(&par->CURSOR[k++], 0, tmp);
143 static void nvidia_write_clut(struct nvidia_par *par,
146 NVWriteDacMask(par, 0xff);
147 NVWriteDacWriteAddr(par, regnum);
148 NVWriteDacData(par, red);
149 NVWriteDacData(par, green);
150 NVWriteDacData(par, blue);
153 static void nvidia_read_clut(struct nvidia_par *par,
156 NVWriteDacMask(par, 0xff);
157 NVWriteDacReadAddr(par, regnum);
158 *red = NVReadDacData(par);
159 *green = NVReadDacData(par);
160 *blue = NVReadDacData(par);
163 static int nvidia_panel_tweak(struct nvidia_par *par,
168 if (par->paneltweak) {
169 tweak = par->paneltweak;
177 if (((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
182 if ((par->Chipset & 0xfff0) == 0x0310)
190 static void nvidia_screen_off(struct nvidia_par *par, int on)
198 tmp = NVReadSeq(par, 0x01);
200 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
201 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
207 tmp = NVReadSeq(par, 0x01);
209 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
210 NVWriteSeq(par, 0x00, 0x03); /* End Reset */
214 static void nvidia_save_vga(struct nvidia_par *par,
220 NVLockUnlock(par, 0);
222 NVUnloadStateExt(par, state);
224 state->misc_output = NVReadMiscOut(par);
227 state->crtc[i] = NVReadCrtc(par, i);
230 state->attr[i] = NVReadAttr(par, i);
233 state->gra[i] = NVReadGr(par, i);
236 state->seq[i] = NVReadSeq(par, i);
242 static void nvidia_write_regs(struct nvidia_par *par,
249 NVLoadStateExt(par, state);
251 NVWriteMiscOut(par, state->misc_output);
257 NVWriteSeq(par, i, state->seq[i]);
261 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
272 NVWriteCrtc(par, i, state->crtc[i]);
280 NVWriteGr(par, i, state->gra[i]);
287 NVWriteAttr(par, i, state->attr[i]);
295 struct nvidia_par *par = info->par;
296 struct _riva_hw_state *state = &par->ModeReg;
322 if (par->FlatPanel == 1) {
361 if (par->Television)
397 if (par->Architecture >= NV_ARCH_10)
398 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
399 par->CursorStart);
410 NVCalcStateExt(par, state, i, info->var.xres_virtual,
414 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
415 if (par->FlatPanel == 1) {
418 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
419 || (par->fpHeight <= info->var.yres)) {
423 if (!par->crtcSync_read) {
424 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
425 par->crtcSync_read = 1;
428 par->PanelTweak = nvidia_panel_tweak(par, state);
436 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
437 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
439 if (par->CRTCnumber) {
440 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
441 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
444 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
445 if (par->twoStagePLL)
446 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
447 } else if (par->twoHeads) {
448 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
449 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
451 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
452 if (par->twoStagePLL)
453 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
461 if (par->alphaCursor) {
462 if ((par->Chipset & 0x0ff0) != 0x0110)
470 if (par->twoHeads) {
471 if ((par->Chipset & 0x0ff0) == 0x0110) {
472 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
474 if (par->FPDither)
477 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
478 if (par->FPDither)
492 struct nvidia_par *par = info->par;
493 struct _riva_hw_state *state = &par->ModeReg;
527 struct nvidia_par *par = info->par;
535 NVShowHideCursor(par, 0);
537 if (par->cursor_reset) {
539 par->cursor_reset = 0;
543 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
553 NV_WR32(par->PRAMDAC, 0x0000300, temp);
591 NVLockUnlock(par, 0);
593 nvidiafb_load_cursor_image(par, data, bg, fg,
601 NVShowHideCursor(par, 1);
610 struct nvidia_par *par = info->par;
614 NVLockUnlock(par, 1);
615 if (!par->FlatPanel || !par->twoHeads)
616 par->FPDither = 0;
618 if (par->FPDither < 0) {
619 if ((par->Chipset & 0x0ff0) == 0x0110)
620 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
623 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
625 par->FPDither ? "enabled" : "disabled");
634 NVLockUnlock(par, 0);
635 if (par->twoHeads) {
636 VGA_WR08(par->PCIO, 0x03D4, 0x44);
637 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
638 NVLockUnlock(par, 0);
641 nvidia_screen_off(par, 1);
643 nvidia_write_regs(par, &par->ModeReg);
644 NVSetStartAddress(par, 0);
651 VGA_WR08(par->PCIO, 0x3d4, 0x46);
652 tmp = VGA_RD08(par->PCIO, 0x3d5);
654 VGA_WR08(par->PCIO, 0x3d5, tmp);
679 par->cursor_reset = 1;
681 nvidia_screen_off(par, 0);
690 NVLockUnlock(par, 0);
699 struct nvidia_par *par = info->par;
721 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
726 nvidia_write_clut(par, regno * 8 + i, red >> 8,
734 nvidia_write_clut(par, regno * 8 + i,
740 nvidia_read_clut(par, regno * 4, &r, &g, &b);
743 nvidia_write_clut(par, regno * 4 + i, r,
748 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
762 struct nvidia_par *par = info->par;
848 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
849 par->fpHeight < var->yres)) {
852 var->xres = par->fpWidth;
853 var->yres = par->fpHeight;
917 struct nvidia_par *par = info->par;
922 NVSetStartAddress(par, total);
929 struct nvidia_par *par = info->par;
932 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
933 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
955 NVWriteSeq(par, 0x01, tmp);
956 NVWriteCrtc(par, 0x1a, vesa);
970 static void save_vga_x86(struct nvidia_par *par)
972 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
975 memset(&par->vgastate, 0, sizeof(par->vgastate));
976 par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS |
978 save_vga(&par->vgastate);
982 static void restore_vga_x86(struct nvidia_par *par)
984 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
987 restore_vga(&par->vgastate);
996 struct nvidia_par *par = info->par;
998 if (!par->open_count) {
999 save_vga_x86(par);
1000 nvidia_save_vga(par, &par->initial_state);
1003 par->open_count++;
1009 struct nvidia_par *par = info->par;
1012 if (!par->open_count) {
1017 if (par->open_count == 1) {
1018 nvidia_write_regs(par, &par->initial_state);
1019 restore_vga_x86(par);
1022 par->open_count--;
1046 struct nvidia_par *par = info->par;
1051 par->pm_state = mesg.event;
1056 nvidia_write_regs(par, &par->SavedReg);
1082 struct nvidia_par *par = info->par;
1086 par->pm_state = PM_EVENT_ON;
1110 struct nvidia_par *par = info->par;
1142 } else if (par->fpWidth && par->fpHeight) {
1146 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1158 info->pseudo_palette = par->pseudo_palette;
1179 switch (par->Architecture) {
1278 struct nvidia_par *par;
1323 par = info->par;
1324 par->pci_dev = pd;
1335 par->FlatPanel = flatpanel;
1338 par->FPDither = fpdither;
1340 par->CRTCnumber = forceCRTC;
1341 par->FpScale = (!noscale);
1342 par->paneltweak = paneltweak;
1343 par->reverse_i2c = reverse_i2c;
1347 par->REGS = REGS;
1349 par->Chipset = Chipset;
1350 par->Architecture = Architecture;
1357 par->FbAddress = nvidiafb_fix.smem_start;
1358 par->FbMapSize = par->RamAmountKBytes * 1024;
1359 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1360 par->FbMapSize = vram * 1024 * 1024;
1363 if (par->FbMapSize > 64 * 1024 * 1024)
1364 par->FbMapSize = 64 * 1024 * 1024;
1366 if(par->Architecture >= NV_ARCH_40)
1367 par->FbUsableSize = par->FbMapSize - (560 * 1024);
1369 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1370 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1372 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1373 par->CursorStart = par->FbUsableSize + (32 * 1024);
1376 par->FbMapSize);
1377 info->screen_size = par->FbUsableSize;
1378 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1385 par->FbStart = info->screen_base;
1388 par->wc_cookie = arch_phys_wc_add(nvidiafb_fix.smem_start,
1389 par->RamAmountKBytes * 1024);
1399 nvidia_save_vga(par, &par->SavedReg);
1409 nvidia_bl_init(par);
1414 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1423 nvidia_delete_i2c_busses(par);
1438 struct nvidia_par *par = info->par;
1442 nvidia_bl_exit(par);
1445 arch_phys_wc_del(par->wc_cookie);
1448 nvidia_delete_i2c_busses(par);
1449 iounmap(par->REGS);