Lines Matching refs:par
60 void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value)
62 VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
63 VGA_WR08(par->PCIO, par->IOBase + 0x05, value);
65 u8 NVReadCrtc(struct nvidia_par *par, u8 index)
67 VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
68 return (VGA_RD08(par->PCIO, par->IOBase + 0x05));
70 void NVWriteGr(struct nvidia_par *par, u8 index, u8 value)
72 VGA_WR08(par->PVIO, VGA_GFX_I, index);
73 VGA_WR08(par->PVIO, VGA_GFX_D, value);
75 u8 NVReadGr(struct nvidia_par *par, u8 index)
77 VGA_WR08(par->PVIO, VGA_GFX_I, index);
78 return (VGA_RD08(par->PVIO, VGA_GFX_D));
80 void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value)
82 VGA_WR08(par->PVIO, VGA_SEQ_I, index);
83 VGA_WR08(par->PVIO, VGA_SEQ_D, value);
85 u8 NVReadSeq(struct nvidia_par *par, u8 index)
87 VGA_WR08(par->PVIO, VGA_SEQ_I, index);
88 return (VGA_RD08(par->PVIO, VGA_SEQ_D));
90 void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value)
93 VGA_RD08(par->PCIO, par->IOBase + 0x0a);
94 if (par->paletteEnabled)
98 VGA_WR08(par->PCIO, VGA_ATT_IW, index);
99 VGA_WR08(par->PCIO, VGA_ATT_W, value);
101 u8 NVReadAttr(struct nvidia_par *par, u8 index)
103 VGA_RD08(par->PCIO, par->IOBase + 0x0a);
104 if (par->paletteEnabled)
108 VGA_WR08(par->PCIO, VGA_ATT_IW, index);
109 return (VGA_RD08(par->PCIO, VGA_ATT_R));
111 void NVWriteMiscOut(struct nvidia_par *par, u8 value)
113 VGA_WR08(par->PVIO, VGA_MIS_W, value);
115 u8 NVReadMiscOut(struct nvidia_par *par)
117 return (VGA_RD08(par->PVIO, VGA_MIS_R));
119 void NVWriteDacMask(struct nvidia_par *par, u8 value)
121 VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
123 void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
125 VGA_WR08(par->PDIO, VGA_PEL_IR, value);
127 void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value)
129 VGA_WR08(par->PDIO, VGA_PEL_IW, value);
131 void NVWriteDacData(struct nvidia_par *par, u8 value)
133 VGA_WR08(par->PDIO, VGA_PEL_D, value);
135 u8 NVReadDacData(struct nvidia_par *par)
137 return (VGA_RD08(par->PDIO, VGA_PEL_D));
140 static int NVIsConnected(struct nvidia_par *par, int output)
142 volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
160 NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140);
161 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
174 NV_WR32(par->PRAMDAC0, 0x0608, dac0_reg608);
182 static void NVSelectHeadRegisters(struct nvidia_par *par, int head)
185 par->PCIO = par->PCIO0 + 0x2000;
186 par->PCRTC = par->PCRTC0 + 0x800;
187 par->PRAMDAC = par->PRAMDAC0 + 0x800;
188 par->PDIO = par->PDIO0 + 0x2000;
190 par->PCIO = par->PCIO0;
191 par->PCRTC = par->PCRTC0;
192 par->PRAMDAC = par->PRAMDAC0;
193 par->PDIO = par->PDIO0;
197 static void nv4GetConfig(struct nvidia_par *par)
199 if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
200 par->RamAmountKBytes =
201 ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
204 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
206 par->RamAmountKBytes = 1024 * 32;
209 par->RamAmountKBytes = 1024 * 4;
212 par->RamAmountKBytes = 1024 * 8;
216 par->RamAmountKBytes = 1024 * 16;
220 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ?
222 par->CURSOR = &par->PRAMIN[0x1E00];
223 par->MinVClockFreqKHz = 12000;
224 par->MaxVClockFreqKHz = 350000;
227 static void nv10GetConfig(struct nvidia_par *par)
230 u32 implementation = par->Chipset & 0x0ff0;
234 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) {
235 NV_WR32(par->PMC, 0x0004, 0x01000001);
240 dev = pci_get_domain_bus_and_slot(pci_domain_nr(par->pci_dev->bus),
242 if ((par->Chipset & 0xffff) == 0x01a0) {
246 par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
247 } else if ((par->Chipset & 0xffff) == 0x01f0) {
251 par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
253 par->RamAmountKBytes =
254 (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;
258 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?
261 if (par->twoHeads && (implementation != 0x0110)) {
262 if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22))
263 par->CrystalFreqKHz = 27000;
266 par->CURSOR = NULL; /* can't set this here */
267 par->MinVClockFreqKHz = 12000;
268 par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000;
273 struct nvidia_par *par = info->par;
275 u16 implementation = par->Chipset & 0x0ff0;
295 par->PRAMIN = par->REGS + (0x00710000 / 4);
296 par->PCRTC0 = par->REGS + (0x00600000 / 4);
297 par->PRAMDAC0 = par->REGS + (0x00680000 / 4);
298 par->PFB = par->REGS + (0x00100000 / 4);
299 par->PFIFO = par->REGS + (0x00002000 / 4);
300 par->PGRAPH = par->REGS + (0x00400000 / 4);
301 par->PEXTDEV = par->REGS + (0x00101000 / 4);
302 par->PTIMER = par->REGS + (0x00009000 / 4);
303 par->PMC = par->REGS + (0x00000000 / 4);
304 par->FIFO = par->REGS + (0x00800000 / 4);
307 par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000;
308 par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000;
309 par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000;
311 par->twoHeads = (par->Architecture >= NV_ARCH_10) &&
316 par->fpScaler = (par->FpScale && par->twoHeads &&
319 par->twoStagePLL = (implementation == 0x0310) ||
320 (implementation == 0x0340) || (par->Architecture >= NV_ARCH_40);
322 par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) &&
325 par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020);
328 switch (par->Chipset & 0xffff) {
383 if (par->Architecture == NV_ARCH_04)
384 nv4GetConfig(par);
386 nv10GetConfig(par);
388 NVSelectHeadRegisters(par, 0);
390 NVLockUnlock(par, 0);
392 par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0;
394 par->Television = 0;
396 nvidia_create_i2c_busses(par);
397 if (!par->twoHeads) {
398 par->CRTCnumber = 0;
408 if ((par->Chipset & 0x0fff) <= 0x0020)
411 VGA_WR08(par->PCIO, 0x03D4, 0x28);
412 if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) {
413 VGA_WR08(par->PCIO, 0x03D4, 0x33);
414 if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01))
425 if (par->FlatPanel == -1) {
426 par->FlatPanel = FlatPanel;
427 par->Television = Television;
430 "specified\n", par->FlatPanel ? "DFP" : "CRT");
441 if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100)
445 if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100)
449 analog_on_A = NVIsConnected(par, 0);
450 analog_on_B = NVIsConnected(par, 1);
458 VGA_WR08(par->PCIO, 0x03D4, 0x44);
459 cr44 = VGA_RD08(par->PCIO, 0x03D5);
461 VGA_WR08(par->PCIO, 0x03D5, 3);
462 NVSelectHeadRegisters(par, 1);
463 NVLockUnlock(par, 0);
465 VGA_WR08(par->PCIO, 0x03D4, 0x28);
466 slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
468 VGA_WR08(par->PCIO, 0x03D4, 0x33);
469 tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
472 VGA_WR08(par->PCIO, 0x03D4, 0x44);
473 VGA_WR08(par->PCIO, 0x03D5, 0);
474 NVSelectHeadRegisters(par, 0);
475 NVLockUnlock(par, 0);
477 VGA_WR08(par->PCIO, 0x03D4, 0x28);
478 slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
480 VGA_WR08(par->PCIO, 0x03D4, 0x33);
481 tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
484 oldhead = NV_RD32(par->PCRTC0, 0x00000860);
485 NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010);
541 if (par->FlatPanel == -1) {
543 par->FlatPanel = FlatPanel;
544 par->Television = Television;
551 par->FlatPanel = 1;
554 par->FlatPanel = 0;
559 "specified\n", par->FlatPanel ? "DFP" : "CRT");
562 if (par->CRTCnumber == -1) {
564 par->CRTCnumber = CRTCnumber;
568 if (par->FlatPanel)
569 par->CRTCnumber = 1;
571 par->CRTCnumber = 0;
573 par->CRTCnumber);
577 "specified\n", par->CRTCnumber);
582 par->FlatPanel) ||
584 !par->FlatPanel)) {
597 !par->FlatPanel) ||
599 par->FlatPanel)) {
607 cr44 = par->CRTCnumber * 0x3;
609 NV_WR32(par->PCRTC0, 0x00000860, oldhead);
611 VGA_WR08(par->PCIO, 0x03D4, 0x44);
612 VGA_WR08(par->PCIO, 0x03D5, cr44);
613 NVSelectHeadRegisters(par, par->CRTCnumber);
617 par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT",
618 par->CRTCnumber);
620 if (par->FlatPanel && !par->Television) {
621 par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1;
622 par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1;
623 par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033;
625 printk("nvidiafb: Panel size is %i x %i\n", par->fpWidth, par->fpHeight);
631 if (!par->FlatPanel || !par->twoHeads)
632 par->FPDither = 0;
634 par->LVDS = 0;
635 if (par->FlatPanel && par->twoHeads) {
636 NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004);
637 if (NV_RD32(par->PRAMDAC0, 0x08b4) & 1)
638 par->LVDS = 1;
639 printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS");