Lines Matching refs:par
57 void NVLockUnlock(struct nvidia_par *par, int Lock)
61 VGA_WR08(par->PCIO, 0x3D4, 0x1F);
62 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
64 VGA_WR08(par->PCIO, 0x3D4, 0x11);
65 cr11 = VGA_RD08(par->PCIO, 0x3D5);
70 VGA_WR08(par->PCIO, 0x3D5, cr11);
73 int NVShowHideCursor(struct nvidia_par *par, int ShowHide)
75 int cur = par->CurrentState->cursor1;
77 par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) |
79 VGA_WR08(par->PCIO, 0x3D4, 0x31);
80 VGA_WR08(par->PCIO, 0x3D5, par->CurrentState->cursor1);
82 if (par->Architecture == NV_ARCH_40)
83 NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300));
141 static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk,
146 if (par->Architecture >= NV_ARCH_40) {
147 pll = NV_RD32(par->PMC, 0x4020);
149 pll = NV_RD32(par->PMC, 0x4024);
152 if (((par->Chipset & 0xfff0) == 0x0290) ||
153 ((par->Chipset & 0xfff0) == 0x0390)) {
160 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
162 pll = NV_RD32(par->PMC, 0x4000);
164 pll = NV_RD32(par->PMC, 0x4004);
170 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
171 } else if (par->twoStagePLL) {
172 pll = NV_RD32(par->PRAMDAC0, 0x0504);
176 pll = NV_RD32(par->PRAMDAC0, 0x0574);
184 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
186 pll = NV_RD32(par->PRAMDAC0, 0x0500);
190 pll = NV_RD32(par->PRAMDAC0, 0x0570);
198 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
200 if (((par->Chipset & 0x0ff0) == 0x0300) ||
201 ((par->Chipset & 0x0ff0) == 0x0330)) {
202 pll = NV_RD32(par->PRAMDAC0, 0x0504);
213 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
215 pll = NV_RD32(par->PRAMDAC0, 0x0500);
226 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
228 pll = NV_RD32(par->PRAMDAC0, 0x0504);
232 *MClk = (N * par->CrystalFreqKHz / M) >> P;
234 pll = NV_RD32(par->PRAMDAC0, 0x0500);
238 *NVClk = (N * par->CrystalFreqKHz / M) >> P;
383 unsigned *lwm, struct nvidia_par *par)
389 nvGetClocks(par, &MClk, &NVClk);
391 cfg1 = NV_RD32(par->PFB, 0x00000204);
395 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
622 struct nvidia_par *par)
628 nvGetClocks(par, &MClk, &NVClk);
630 cfg1 = NV_RD32(par->PFB, 0x0204);
634 sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0;
635 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
656 struct nvidia_par *par,
668 nvGetClocks(par, &MClk, &NVClk);
680 struct nvidia_par *par)
686 int domain = pci_domain_nr(par->pci_dev->bus);
688 if ((par->Chipset & 0x0FF0) == 0x01A0) {
703 pll = NV_RD32(par->PRAMDAC0, 0x0500);
707 NVClk = (N * par->CrystalFreqKHz / M) >> P;
767 int *clockOut, u32 * pllOut, struct nvidia_par *par)
778 if (par->CrystalFreqKHz == 13500) {
790 N = ((VClk << P) * M) / par->CrystalFreqKHz;
793 ((par->CrystalFreqKHz * N) /
814 u32 * pllBOut, struct nvidia_par *par)
831 (par->CrystalFreqKHz << 2);
834 (((par->CrystalFreqKHz << 2) * N) /
856 void NVCalcStateExt(struct nvidia_par *par,
873 if (par->twoStagePLL)
875 par);
877 CalcVClock(dotClock, &VClk, &state->pll, par);
879 switch (par->Architecture) {
884 &(state->arbitration1), par);
896 if (!par->FlatPanel)
897 state->control = NV_RD32(par->PRAMDAC0, 0x0580) &
904 if ((par->Chipset & 0xfff0) == 0x0240 ||
905 (par->Chipset & 0xfff0) == 0x03d0) {
908 } else if (((par->Chipset & 0xffff) == 0x01A0) ||
909 ((par->Chipset & 0xffff) == 0x01f0)) {
914 par);
915 } else if (par->Architecture < NV_ARCH_30) {
920 par);
922 nv30UpdateArbitrationSettings(par,
927 state->cursor0 = 0x80 | (par->CursorStart >> 17);
928 state->cursor1 = (par->CursorStart >> 11) << 2;
929 state->cursor2 = par->CursorStart >> 24;
933 state->config = NV_RD32(par->PFB, 0x00000200);
946 void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
950 NV_WR32(par->PMC, 0x0140, 0x00000000);
951 NV_WR32(par->PMC, 0x0200, 0xFFFF00FF);
952 NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF);
954 NV_WR32(par->PTIMER, 0x0200 * 4, 0x00000008);
955 NV_WR32(par->PTIMER, 0x0210 * 4, 0x00000003);
956 NV_WR32(par->PTIMER, 0x0140 * 4, 0x00000000);
957 NV_WR32(par->PTIMER, 0x0100 * 4, 0xFFFFFFFF);
959 if (par->Architecture == NV_ARCH_04) {
961 NV_WR32(par->PFB, 0x0200, state->config);
962 } else if ((par->Architecture < NV_ARCH_40) ||
963 (par->Chipset & 0xfff0) == 0x0040) {
965 NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0);
966 NV_WR32(par->PFB, 0x0244 + (i * 0x10),
967 par->FbMapSize - 1);
972 if (((par->Chipset & 0xfff0) == 0x0090) ||
973 ((par->Chipset & 0xfff0) == 0x01D0) ||
974 ((par->Chipset & 0xfff0) == 0x0290) ||
975 ((par->Chipset & 0xfff0) == 0x0390) ||
976 ((par->Chipset & 0xfff0) == 0x03D0))
979 NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
980 NV_WR32(par->PFB, 0x0604 + (i * 0x10),
981 par->FbMapSize - 1);
985 if (par->Architecture >= NV_ARCH_40) {
986 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
987 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x00101202);
988 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
989 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x00101204);
990 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
991 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x00101206);
992 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
993 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x00101208);
994 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
995 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x0010120A);
996 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
997 NV_WR32(par->PRAMIN, 0x000B * 4, 0x0010120C);
998 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
999 NV_WR32(par->PRAMIN, 0x000D * 4, 0x0010120E);
1000 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
1001 NV_WR32(par->PRAMIN, 0x000F * 4, 0x00101210);
1002 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
1003 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
1004 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
1005 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x02080062);
1006 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
1007 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00001200);
1008 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00001200);
1009 NV_WR32(par->PRAMIN, 0x080C * 4, 0x00000000);
1010 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000000);
1011 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x02080043);
1012 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
1013 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
1014 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
1015 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x00000000);
1016 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
1017 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x02080044);
1018 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x02000000);
1019 NV_WR32(par->PRAMIN, 0x081A * 4, 0x00000000);
1020 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
1021 NV_WR32(par->PRAMIN, 0x081C * 4, 0x00000000);
1022 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000000);
1023 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x02080019);
1024 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
1025 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x00000000);
1026 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
1027 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00000000);
1028 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00000000);
1029 NV_WR32(par->PRAMIN, 0x0828 * 4, 0x020A005C);
1030 NV_WR32(par->PRAMIN, 0x0829 * 4, 0x00000000);
1031 NV_WR32(par->PRAMIN, 0x082A * 4, 0x00000000);
1032 NV_WR32(par->PRAMIN, 0x082B * 4, 0x00000000);
1033 NV_WR32(par->PRAMIN, 0x082C * 4, 0x00000000);
1034 NV_WR32(par->PRAMIN, 0x082D * 4, 0x00000000);
1035 NV_WR32(par->PRAMIN, 0x0830 * 4, 0x0208009F);
1036 NV_WR32(par->PRAMIN, 0x0831 * 4, 0x00000000);
1037 NV_WR32(par->PRAMIN, 0x0832 * 4, 0x00001200);
1038 NV_WR32(par->PRAMIN, 0x0833 * 4, 0x00001200);
1039 NV_WR32(par->PRAMIN, 0x0834 * 4, 0x00000000);
1040 NV_WR32(par->PRAMIN, 0x0835 * 4, 0x00000000);
1041 NV_WR32(par->PRAMIN, 0x0838 * 4, 0x0208004A);
1042 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x02000000);
1043 NV_WR32(par->PRAMIN, 0x083A * 4, 0x00000000);
1044 NV_WR32(par->PRAMIN, 0x083B * 4, 0x00000000);
1045 NV_WR32(par->PRAMIN, 0x083C * 4, 0x00000000);
1046 NV_WR32(par->PRAMIN, 0x083D * 4, 0x00000000);
1047 NV_WR32(par->PRAMIN, 0x0840 * 4, 0x02080077);
1048 NV_WR32(par->PRAMIN, 0x0841 * 4, 0x00000000);
1049 NV_WR32(par->PRAMIN, 0x0842 * 4, 0x00001200);
1050 NV_WR32(par->PRAMIN, 0x0843 * 4, 0x00001200);
1051 NV_WR32(par->PRAMIN, 0x0844 * 4, 0x00000000);
1052 NV_WR32(par->PRAMIN, 0x0845 * 4, 0x00000000);
1053 NV_WR32(par->PRAMIN, 0x084C * 4, 0x00003002);
1054 NV_WR32(par->PRAMIN, 0x084D * 4, 0x00007FFF);
1055 NV_WR32(par->PRAMIN, 0x084E * 4,
1056 par->FbUsableSize | 0x00000002);
1059 NV_WR32(par->PRAMIN, 0x080A * 4,
1060 NV_RD32(par->PRAMIN, 0x080A * 4) | 0x01000000);
1061 NV_WR32(par->PRAMIN, 0x0812 * 4,
1062 NV_RD32(par->PRAMIN, 0x0812 * 4) | 0x01000000);
1063 NV_WR32(par->PRAMIN, 0x081A * 4,
1064 NV_RD32(par->PRAMIN, 0x081A * 4) | 0x01000000);
1065 NV_WR32(par->PRAMIN, 0x0822 * 4,
1066 NV_RD32(par->PRAMIN, 0x0822 * 4) | 0x01000000);
1067 NV_WR32(par->PRAMIN, 0x082A * 4,
1068 NV_RD32(par->PRAMIN, 0x082A * 4) | 0x01000000);
1069 NV_WR32(par->PRAMIN, 0x0832 * 4,
1070 NV_RD32(par->PRAMIN, 0x0832 * 4) | 0x01000000);
1071 NV_WR32(par->PRAMIN, 0x083A * 4,
1072 NV_RD32(par->PRAMIN, 0x083A * 4) | 0x01000000);
1073 NV_WR32(par->PRAMIN, 0x0842 * 4,
1074 NV_RD32(par->PRAMIN, 0x0842 * 4) | 0x01000000);
1075 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x01000000);
1076 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x01000000);
1079 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
1080 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x80011201);
1081 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
1082 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x80011202);
1083 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
1084 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x80011203);
1085 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
1086 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x80011204);
1087 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
1088 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x80011205);
1089 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
1090 NV_WR32(par->PRAMIN, 0x000B * 4, 0x80011206);
1091 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
1092 NV_WR32(par->PRAMIN, 0x000D * 4, 0x80011207);
1093 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
1094 NV_WR32(par->PRAMIN, 0x000F * 4, 0x80011208);
1095 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
1096 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
1097 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
1098 NV_WR32(par->PRAMIN, 0x0803 * 4, 0x00000002);
1099 if (par->Architecture >= NV_ARCH_10)
1100 NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008062);
1102 NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008042);
1103 NV_WR32(par->PRAMIN, 0x0805 * 4, 0x00000000);
1104 NV_WR32(par->PRAMIN, 0x0806 * 4, 0x12001200);
1105 NV_WR32(par->PRAMIN, 0x0807 * 4, 0x00000000);
1106 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x01008043);
1107 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
1108 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00000000);
1109 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00000000);
1110 NV_WR32(par->PRAMIN, 0x080C * 4, 0x01008044);
1111 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000002);
1112 NV_WR32(par->PRAMIN, 0x080E * 4, 0x00000000);
1113 NV_WR32(par->PRAMIN, 0x080F * 4, 0x00000000);
1114 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x01008019);
1115 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
1116 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
1117 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
1118 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x0100A05C);
1119 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
1120 NV_WR32(par->PRAMIN, 0x0816 * 4, 0x00000000);
1121 NV_WR32(par->PRAMIN, 0x0817 * 4, 0x00000000);
1122 if (par->WaitVSyncPossible)
1123 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100809F);
1125 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100805F);
1126 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x00000000);
1127 NV_WR32(par->PRAMIN, 0x081A * 4, 0x12001200);
1128 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
1129 NV_WR32(par->PRAMIN, 0x081C * 4, 0x0100804A);
1130 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000002);
1131 NV_WR32(par->PRAMIN, 0x081E * 4, 0x00000000);
1132 NV_WR32(par->PRAMIN, 0x081F * 4, 0x00000000);
1133 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x01018077);
1134 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
1135 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x12001200);
1136 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
1137 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00003002);
1138 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00007FFF);
1139 NV_WR32(par->PRAMIN, 0x0826 * 4,
1140 par->FbUsableSize | 0x00000002);
1141 NV_WR32(par->PRAMIN, 0x0827 * 4, 0x00000002);
1143 NV_WR32(par->PRAMIN, 0x0804 * 4,
1144 NV_RD32(par->PRAMIN, 0x0804 * 4) | 0x00080000);
1145 NV_WR32(par->PRAMIN, 0x0808 * 4,
1146 NV_RD32(par->PRAMIN, 0x0808 * 4) | 0x00080000);
1147 NV_WR32(par->PRAMIN, 0x080C * 4,
1148 NV_RD32(par->PRAMIN, 0x080C * 4) | 0x00080000);
1149 NV_WR32(par->PRAMIN, 0x0810 * 4,
1150 NV_RD32(par->PRAMIN, 0x0810 * 4) | 0x00080000);
1151 NV_WR32(par->PRAMIN, 0x0814 * 4,
1152 NV_RD32(par->PRAMIN, 0x0814 * 4) | 0x00080000);
1153 NV_WR32(par->PRAMIN, 0x0818 * 4,
1154 NV_RD32(par->PRAMIN, 0x0818 * 4) | 0x00080000);
1155 NV_WR32(par->PRAMIN, 0x081C * 4,
1156 NV_RD32(par->PRAMIN, 0x081C * 4) | 0x00080000);
1157 NV_WR32(par->PRAMIN, 0x0820 * 4,
1158 NV_RD32(par->PRAMIN, 0x0820 * 4) | 0x00080000);
1159 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000001);
1160 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000001);
1163 if (par->Architecture < NV_ARCH_10) {
1164 if ((par->Chipset & 0x0fff) == 0x0020) {
1165 NV_WR32(par->PRAMIN, 0x0824 * 4,
1166 NV_RD32(par->PRAMIN, 0x0824 * 4) | 0x00020000);
1167 NV_WR32(par->PRAMIN, 0x0826 * 4,
1168 NV_RD32(par->PRAMIN,
1169 0x0826 * 4) + par->FbAddress);
1171 NV_WR32(par->PGRAPH, 0x0080, 0x000001FF);
1172 NV_WR32(par->PGRAPH, 0x0080, 0x1230C000);
1173 NV_WR32(par->PGRAPH, 0x0084, 0x72111101);
1174 NV_WR32(par->PGRAPH, 0x0088, 0x11D5F071);
1175 NV_WR32(par->PGRAPH, 0x008C, 0x0004FF31);
1176 NV_WR32(par->PGRAPH, 0x008C, 0x4004FF31);
1177 NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1178 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1179 NV_WR32(par->PGRAPH, 0x0170, 0x10010100);
1180 NV_WR32(par->PGRAPH, 0x0710, 0xFFFFFFFF);
1181 NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1182 NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1183 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1185 NV_WR32(par->PGRAPH, 0x0080, 0xFFFFFFFF);
1186 NV_WR32(par->PGRAPH, 0x0080, 0x00000000);
1188 NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1189 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1190 NV_WR32(par->PGRAPH, 0x0144, 0x10010100);
1191 NV_WR32(par->PGRAPH, 0x0714, 0xFFFFFFFF);
1192 NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1193 NV_WR32(par->PGRAPH, 0x0710,
1194 NV_RD32(par->PGRAPH, 0x0710) & 0x0007ff00);
1195 NV_WR32(par->PGRAPH, 0x0710,
1196 NV_RD32(par->PGRAPH, 0x0710) | 0x00020100);
1198 if (par->Architecture == NV_ARCH_10) {
1199 NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1200 NV_WR32(par->PGRAPH, 0x0088, 0x24E00810);
1201 NV_WR32(par->PGRAPH, 0x008C, 0x55DE0030);
1204 NV_WR32(&par->PGRAPH[(0x0B00 / 4) + i], 0,
1205 NV_RD32(&par->PFB[(0x0240 / 4) + i],
1208 NV_WR32(par->PGRAPH, 0x640, 0);
1209 NV_WR32(par->PGRAPH, 0x644, 0);
1210 NV_WR32(par->PGRAPH, 0x684, par->FbMapSize - 1);
1211 NV_WR32(par->PGRAPH, 0x688, par->FbMapSize - 1);
1213 NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1214 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1216 if (par->Architecture >= NV_ARCH_40) {
1217 NV_WR32(par->PGRAPH, 0x0084, 0x401287c0);
1218 NV_WR32(par->PGRAPH, 0x008C, 0x60de8051);
1219 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1220 NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f);
1221 NV_WR32(par->PGRAPH, 0x0bc4,
1222 NV_RD32(par->PGRAPH, 0x0bc4) |
1225 j = NV_RD32(par->REGS, 0x1540) & 0xff;
1229 NV_WR32(par->PGRAPH, 0x5000, i);
1232 if ((par->Chipset & 0xfff0) == 0x0040) {
1233 NV_WR32(par->PGRAPH, 0x09b0,
1235 NV_WR32(par->PGRAPH, 0x09b4,
1238 NV_WR32(par->PGRAPH, 0x0820,
1240 NV_WR32(par->PGRAPH, 0x0824,
1244 switch (par->Chipset & 0xfff0) {
1247 NV_WR32(par->PGRAPH, 0x09b8,
1249 NV_WR32(par->PGRAPH, 0x09bc,
1251 NV_WR32(par->PFB, 0x033C,
1252 NV_RD32(par->PFB, 0x33C) &
1257 NV_WR32(par->PGRAPH, 0x0828,
1259 NV_WR32(par->PGRAPH, 0x082C,
1266 NV_WR32(par->PMC, 0x1700,
1267 NV_RD32(par->PFB, 0x020C));
1268 NV_WR32(par->PMC, 0x1704, 0);
1269 NV_WR32(par->PMC, 0x1708, 0);
1270 NV_WR32(par->PMC, 0x170C,
1271 NV_RD32(par->PFB, 0x020C));
1272 NV_WR32(par->PGRAPH, 0x0860, 0);
1273 NV_WR32(par->PGRAPH, 0x0864, 0);
1274 NV_WR32(par->PRAMDAC, 0x0608,
1275 NV_RD32(par->PRAMDAC,
1279 NV_WR32(par->PGRAPH, 0x0828,
1281 NV_WR32(par->PGRAPH, 0x082C,
1285 NV_WR32(par->PGRAPH, 0x0860, 0);
1286 NV_WR32(par->PGRAPH, 0x0864, 0);
1287 NV_WR32(par->PRAMDAC, 0x0608,
1288 NV_RD32(par->PRAMDAC, 0x0608) |
1294 NV_WR32(par->PRAMDAC, 0x0608,
1295 NV_RD32(par->PRAMDAC, 0x0608) |
1297 NV_WR32(par->PGRAPH, 0x0828,
1299 NV_WR32(par->PGRAPH, 0x082C,
1306 NV_WR32(par->PGRAPH, 0x0b38, 0x2ffff800);
1307 NV_WR32(par->PGRAPH, 0x0b3c, 0x00006000);
1308 NV_WR32(par->PGRAPH, 0x032C, 0x01000000);
1309 NV_WR32(par->PGRAPH, 0x0220, 0x00001200);
1310 } else if (par->Architecture == NV_ARCH_30) {
1311 NV_WR32(par->PGRAPH, 0x0084, 0x40108700);
1312 NV_WR32(par->PGRAPH, 0x0890, 0x00140000);
1313 NV_WR32(par->PGRAPH, 0x008C, 0xf00e0431);
1314 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1315 NV_WR32(par->PGRAPH, 0x0610, 0xf04b1f36);
1316 NV_WR32(par->PGRAPH, 0x0B80, 0x1002d888);
1317 NV_WR32(par->PGRAPH, 0x0B88, 0x62ff007f);
1319 NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1320 NV_WR32(par->PGRAPH, 0x008C, 0xF20E0431);
1321 NV_WR32(par->PGRAPH, 0x0090, 0x00000000);
1322 NV_WR32(par->PGRAPH, 0x009C, 0x00000040);
1324 if ((par->Chipset & 0x0ff0) >= 0x0250) {
1325 NV_WR32(par->PGRAPH, 0x0890,
1327 NV_WR32(par->PGRAPH, 0x0610,
1329 NV_WR32(par->PGRAPH, 0x0B80,
1331 NV_WR32(par->PGRAPH, 0x0B84,
1333 NV_WR32(par->PGRAPH, 0x0098,
1335 NV_WR32(par->PGRAPH, 0x0B88,
1338 NV_WR32(par->PGRAPH, 0x0880,
1340 NV_WR32(par->PGRAPH, 0x0094,
1342 NV_WR32(par->PGRAPH, 0x0B80,
1344 NV_WR32(par->PGRAPH, 0x0B84,
1346 NV_WR32(par->PGRAPH, 0x0098,
1348 NV_WR32(par->PGRAPH, 0x0750,
1350 NV_WR32(par->PGRAPH, 0x0754,
1352 NV_WR32(par->PGRAPH, 0x0750,
1354 NV_WR32(par->PGRAPH, 0x0754,
1359 if ((par->Architecture < NV_ARCH_40) ||
1360 ((par->Chipset & 0xfff0) == 0x0040)) {
1362 NV_WR32(par->PGRAPH, 0x0900 + i*4,
1363 NV_RD32(par->PFB, 0x0240 +i*4));
1364 NV_WR32(par->PGRAPH, 0x6900 + i*4,
1365 NV_RD32(par->PFB, 0x0240 +i*4));
1368 if (((par->Chipset & 0xfff0) == 0x0090) ||
1369 ((par->Chipset & 0xfff0) == 0x01D0) ||
1370 ((par->Chipset & 0xfff0) == 0x0290) ||
1371 ((par->Chipset & 0xfff0) == 0x0390) ||
1372 ((par->Chipset & 0xfff0) == 0x03D0)) {
1374 NV_WR32(par->PGRAPH,
1376 NV_RD32(par->PFB,
1378 NV_WR32(par->PGRAPH,
1380 NV_RD32(par->PFB,
1385 NV_WR32(par->PGRAPH,
1387 NV_RD32(par->PFB,
1389 if(((par->Chipset & 0xfff0)
1391 ((par->Chipset & 0xfff0)
1393 ((par->Chipset & 0xfff0)
1395 NV_WR32(par->PGRAPH,
1397 NV_RD32(par->PFB,
1403 if (par->Architecture >= NV_ARCH_40) {
1404 if ((par->Chipset & 0xfff0) == 0x0040) {
1405 NV_WR32(par->PGRAPH, 0x09A4,
1406 NV_RD32(par->PFB, 0x0200));
1407 NV_WR32(par->PGRAPH, 0x09A8,
1408 NV_RD32(par->PFB, 0x0204));
1409 NV_WR32(par->PGRAPH, 0x69A4,
1410 NV_RD32(par->PFB, 0x0200));
1411 NV_WR32(par->PGRAPH, 0x69A8,
1412 NV_RD32(par->PFB, 0x0204));
1414 NV_WR32(par->PGRAPH, 0x0820, 0);
1415 NV_WR32(par->PGRAPH, 0x0824, 0);
1416 NV_WR32(par->PGRAPH, 0x0864,
1417 par->FbMapSize - 1);
1418 NV_WR32(par->PGRAPH, 0x0868,
1419 par->FbMapSize - 1);
1421 if ((par->Chipset & 0xfff0) == 0x0090 ||
1422 (par->Chipset & 0xfff0) == 0x01D0 ||
1423 (par->Chipset & 0xfff0) == 0x0290 ||
1424 (par->Chipset & 0xfff0) == 0x0390) {
1425 NV_WR32(par->PGRAPH, 0x0DF0,
1426 NV_RD32(par->PFB, 0x0200));
1427 NV_WR32(par->PGRAPH, 0x0DF4,
1428 NV_RD32(par->PFB, 0x0204));
1430 NV_WR32(par->PGRAPH, 0x09F0,
1431 NV_RD32(par->PFB, 0x0200));
1432 NV_WR32(par->PGRAPH, 0x09F4,
1433 NV_RD32(par->PFB, 0x0204));
1435 NV_WR32(par->PGRAPH, 0x69F0,
1436 NV_RD32(par->PFB, 0x0200));
1437 NV_WR32(par->PGRAPH, 0x69F4,
1438 NV_RD32(par->PFB, 0x0204));
1440 NV_WR32(par->PGRAPH, 0x0840, 0);
1441 NV_WR32(par->PGRAPH, 0x0844, 0);
1442 NV_WR32(par->PGRAPH, 0x08a0,
1443 par->FbMapSize - 1);
1444 NV_WR32(par->PGRAPH, 0x08a4,
1445 par->FbMapSize - 1);
1448 NV_WR32(par->PGRAPH, 0x09A4,
1449 NV_RD32(par->PFB, 0x0200));
1450 NV_WR32(par->PGRAPH, 0x09A8,
1451 NV_RD32(par->PFB, 0x0204));
1452 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0000);
1453 NV_WR32(par->PGRAPH, 0x0754,
1454 NV_RD32(par->PFB, 0x0200));
1455 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0004);
1456 NV_WR32(par->PGRAPH, 0x0754,
1457 NV_RD32(par->PFB, 0x0204));
1459 NV_WR32(par->PGRAPH, 0x0820, 0);
1460 NV_WR32(par->PGRAPH, 0x0824, 0);
1461 NV_WR32(par->PGRAPH, 0x0864,
1462 par->FbMapSize - 1);
1463 NV_WR32(par->PGRAPH, 0x0868,
1464 par->FbMapSize - 1);
1466 NV_WR32(par->PGRAPH, 0x0B20, 0x00000000);
1467 NV_WR32(par->PGRAPH, 0x0B04, 0xFFFFFFFF);
1470 NV_WR32(par->PGRAPH, 0x053C, 0);
1471 NV_WR32(par->PGRAPH, 0x0540, 0);
1472 NV_WR32(par->PGRAPH, 0x0544, 0x00007FFF);
1473 NV_WR32(par->PGRAPH, 0x0548, 0x00007FFF);
1475 NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000000);
1476 NV_WR32(par->PFIFO, 0x0141 * 4, 0x00000001);
1477 NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000000);
1478 NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000000);
1479 if (par->Architecture >= NV_ARCH_40)
1480 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00010000);
1482 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00000100);
1483 NV_WR32(par->PFIFO, 0x0490 * 4, 0x00000000);
1484 NV_WR32(par->PFIFO, 0x0491 * 4, 0x00000000);
1485 if (par->Architecture >= NV_ARCH_40)
1486 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001213);
1488 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001209);
1489 NV_WR32(par->PFIFO, 0x0400 * 4, 0x00000000);
1490 NV_WR32(par->PFIFO, 0x0414 * 4, 0x00000000);
1491 NV_WR32(par->PFIFO, 0x0084 * 4, 0x03000100);
1492 NV_WR32(par->PFIFO, 0x0085 * 4, 0x00000110);
1493 NV_WR32(par->PFIFO, 0x0086 * 4, 0x00000112);
1494 NV_WR32(par->PFIFO, 0x0143 * 4, 0x0000FFFF);
1495 NV_WR32(par->PFIFO, 0x0496 * 4, 0x0000FFFF);
1496 NV_WR32(par->PFIFO, 0x0050 * 4, 0x00000000);
1497 NV_WR32(par->PFIFO, 0x0040 * 4, 0xFFFFFFFF);
1498 NV_WR32(par->PFIFO, 0x0415 * 4, 0x00000001);
1499 NV_WR32(par->PFIFO, 0x048C * 4, 0x00000000);
1500 NV_WR32(par->PFIFO, 0x04A0 * 4, 0x00000000);
1502 NV_WR32(par->PFIFO, 0x0489 * 4, 0x800F0078);
1504 NV_WR32(par->PFIFO, 0x0489 * 4, 0x000F0078);
1506 NV_WR32(par->PFIFO, 0x0488 * 4, 0x00000001);
1507 NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000001);
1508 NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000001);
1509 NV_WR32(par->PFIFO, 0x0495 * 4, 0x00000001);
1510 NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000001);
1513 par->CurrentState = NULL;
1517 if (par->Architecture >= NV_ARCH_10) {
1518 if (par->twoHeads) {
1519 NV_WR32(par->PCRTC0, 0x0860, state->head);
1520 NV_WR32(par->PCRTC0, 0x2860, state->head2);
1522 NV_WR32(par->PRAMDAC, 0x0404, NV_RD32(par->PRAMDAC, 0x0404) |
1525 NV_WR32(par->PMC, 0x8704, 1);
1526 NV_WR32(par->PMC, 0x8140, 0);
1527 NV_WR32(par->PMC, 0x8920, 0);
1528 NV_WR32(par->PMC, 0x8924, 0);
1529 NV_WR32(par->PMC, 0x8908, par->FbMapSize - 1);
1530 NV_WR32(par->PMC, 0x890C, par->FbMapSize - 1);
1531 NV_WR32(par->PMC, 0x1588, 0);
1533 NV_WR32(par->PCRTC, 0x0810, state->cursorConfig);
1534 NV_WR32(par->PCRTC, 0x0830, state->displayV - 3);
1535 NV_WR32(par->PCRTC, 0x0834, state->displayV - 1);
1537 if (par->FlatPanel) {
1538 if ((par->Chipset & 0x0ff0) == 0x0110) {
1539 NV_WR32(par->PRAMDAC, 0x0528, state->dither);
1540 } else if (par->twoHeads) {
1541 NV_WR32(par->PRAMDAC, 0x083C, state->dither);
1544 VGA_WR08(par->PCIO, 0x03D4, 0x53);
1545 VGA_WR08(par->PCIO, 0x03D5, state->timingH);
1546 VGA_WR08(par->PCIO, 0x03D4, 0x54);
1547 VGA_WR08(par->PCIO, 0x03D5, state->timingV);
1548 VGA_WR08(par->PCIO, 0x03D4, 0x21);
1549 VGA_WR08(par->PCIO, 0x03D5, 0xfa);
1552 VGA_WR08(par->PCIO, 0x03D4, 0x41);
1553 VGA_WR08(par->PCIO, 0x03D5, state->extra);
1556 VGA_WR08(par->PCIO, 0x03D4, 0x19);
1557 VGA_WR08(par->PCIO, 0x03D5, state->repaint0);
1558 VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1559 VGA_WR08(par->PCIO, 0x03D5, state->repaint1);
1560 VGA_WR08(par->PCIO, 0x03D4, 0x25);
1561 VGA_WR08(par->PCIO, 0x03D5, state->screen);
1562 VGA_WR08(par->PCIO, 0x03D4, 0x28);
1563 VGA_WR08(par->PCIO, 0x03D5, state->pixel);
1564 VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1565 VGA_WR08(par->PCIO, 0x03D5, state->horiz);
1566 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1567 VGA_WR08(par->PCIO, 0x03D5, state->fifo);
1568 VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1569 VGA_WR08(par->PCIO, 0x03D5, state->arbitration0);
1570 VGA_WR08(par->PCIO, 0x03D4, 0x20);
1571 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1);
1573 if(par->Architecture >= NV_ARCH_30) {
1574 VGA_WR08(par->PCIO, 0x03D4, 0x47);
1575 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1 >> 8);
1578 VGA_WR08(par->PCIO, 0x03D4, 0x30);
1579 VGA_WR08(par->PCIO, 0x03D5, state->cursor0);
1580 VGA_WR08(par->PCIO, 0x03D4, 0x31);
1581 VGA_WR08(par->PCIO, 0x03D5, state->cursor1);
1582 VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1583 VGA_WR08(par->PCIO, 0x03D5, state->cursor2);
1584 VGA_WR08(par->PCIO, 0x03D4, 0x39);
1585 VGA_WR08(par->PCIO, 0x03D5, state->interlace);
1587 if (!par->FlatPanel) {
1588 if (par->Architecture >= NV_ARCH_40)
1589 NV_WR32(par->PRAMDAC0, 0x0580, state->control);
1591 NV_WR32(par->PRAMDAC0, 0x050C, state->pllsel);
1592 NV_WR32(par->PRAMDAC0, 0x0508, state->vpll);
1593 if (par->twoHeads)
1594 NV_WR32(par->PRAMDAC0, 0x0520, state->vpll2);
1595 if (par->twoStagePLL) {
1596 NV_WR32(par->PRAMDAC0, 0x0578, state->vpllB);
1597 NV_WR32(par->PRAMDAC0, 0x057C, state->vpll2B);
1600 NV_WR32(par->PRAMDAC, 0x0848, state->scale);
1601 NV_WR32(par->PRAMDAC, 0x0828, state->crtcSync +
1602 par->PanelTweak);
1605 NV_WR32(par->PRAMDAC, 0x0600, state->general);
1607 NV_WR32(par->PCRTC, 0x0140, 0);
1608 NV_WR32(par->PCRTC, 0x0100, 1);
1610 par->CurrentState = state;
1613 void NVUnloadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) {
1614 VGA_WR08(par->PCIO, 0x03D4, 0x19);
1615 state->repaint0 = VGA_RD08(par->PCIO, 0x03D5);
1616 VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1617 state->repaint1 = VGA_RD08(par->PCIO, 0x03D5);
1618 VGA_WR08(par->PCIO, 0x03D4, 0x25);
1619 state->screen = VGA_RD08(par->PCIO, 0x03D5);
1620 VGA_WR08(par->PCIO, 0x03D4, 0x28);
1621 state->pixel = VGA_RD08(par->PCIO, 0x03D5);
1622 VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1623 state->horiz = VGA_RD08(par->PCIO, 0x03D5);
1624 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1625 state->fifo = VGA_RD08(par->PCIO, 0x03D5);
1626 VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1627 state->arbitration0 = VGA_RD08(par->PCIO, 0x03D5);
1628 VGA_WR08(par->PCIO, 0x03D4, 0x20);
1629 state->arbitration1 = VGA_RD08(par->PCIO, 0x03D5);
1631 if(par->Architecture >= NV_ARCH_30) {
1632 VGA_WR08(par->PCIO, 0x03D4, 0x47);
1633 state->arbitration1 |= (VGA_RD08(par->PCIO, 0x03D5) & 1) << 8;
1636 VGA_WR08(par->PCIO, 0x03D4, 0x30);
1637 state->cursor0 = VGA_RD08(par->PCIO, 0x03D5);
1638 VGA_WR08(par->PCIO, 0x03D4, 0x31);
1639 state->cursor1 = VGA_RD08(par->PCIO, 0x03D5);
1640 VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1641 state->cursor2 = VGA_RD08(par->PCIO, 0x03D5);
1642 VGA_WR08(par->PCIO, 0x03D4, 0x39);
1643 state->interlace = VGA_RD08(par->PCIO, 0x03D5);
1644 state->vpll = NV_RD32(par->PRAMDAC0, 0x0508);
1645 if (par->twoHeads)
1646 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
1647 if (par->twoStagePLL) {
1648 state->vpllB = NV_RD32(par->PRAMDAC0, 0x0578);
1649 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
1651 state->pllsel = NV_RD32(par->PRAMDAC0, 0x050C);
1652 state->general = NV_RD32(par->PRAMDAC, 0x0600);
1653 state->scale = NV_RD32(par->PRAMDAC, 0x0848);
1654 state->config = NV_RD32(par->PFB, 0x0200);
1656 if (par->Architecture >= NV_ARCH_40 && !par->FlatPanel)
1657 state->control = NV_RD32(par->PRAMDAC0, 0x0580);
1659 if (par->Architecture >= NV_ARCH_10) {
1660 if (par->twoHeads) {
1661 state->head = NV_RD32(par->PCRTC0, 0x0860);
1662 state->head2 = NV_RD32(par->PCRTC0, 0x2860);
1663 VGA_WR08(par->PCIO, 0x03D4, 0x44);
1664 state->crtcOwner = VGA_RD08(par->PCIO, 0x03D5);
1666 VGA_WR08(par->PCIO, 0x03D4, 0x41);
1667 state->extra = VGA_RD08(par->PCIO, 0x03D5);
1668 state->cursorConfig = NV_RD32(par->PCRTC, 0x0810);
1670 if ((par->Chipset & 0x0ff0) == 0x0110) {
1671 state->dither = NV_RD32(par->PRAMDAC, 0x0528);
1672 } else if (par->twoHeads) {
1673 state->dither = NV_RD32(par->PRAMDAC, 0x083C);
1676 if (par->FlatPanel) {
1677 VGA_WR08(par->PCIO, 0x03D4, 0x53);
1678 state->timingH = VGA_RD08(par->PCIO, 0x03D5);
1679 VGA_WR08(par->PCIO, 0x03D4, 0x54);
1680 state->timingV = VGA_RD08(par->PCIO, 0x03D5);
1685 void NVSetStartAddress(struct nvidia_par *par, u32 start)
1687 NV_WR32(par->PCRTC, 0x800, start);