Lines Matching defs:par
145 static inline void write_le32(int regindex, u32 val, const struct neofb_par *par)
147 writel(val, par->neo2200 + par->cursorOff + regindex);
203 struct neofb_par *par, long freq)
233 par->VCLK3NumeratorLow = n_best;
234 par->VCLK3NumeratorHigh = (f_best << 7);
236 par->VCLK3NumeratorLow = n_best | (f_best << 7);
238 par->VCLK3Denominator = d_best;
243 par->VCLK3NumeratorLow,
244 par->VCLK3NumeratorHigh,
245 par->VCLK3Denominator, f_best_diff);
256 struct neofb_par *par)
264 par->MiscOutReg = 0x23;
267 par->MiscOutReg |= 0x40;
270 par->MiscOutReg |= 0x80;
275 par->Sequencer[0] = 0x00;
276 par->Sequencer[1] = 0x01;
277 par->Sequencer[2] = 0x0F;
278 par->Sequencer[3] = 0x00; /* Font select */
279 par->Sequencer[4] = 0x0E; /* Misc */
284 par->CRTC[0] = htotal - 5;
285 par->CRTC[1] = (var->xres >> 3) - 1;
286 par->CRTC[2] = (var->xres >> 3) - 1;
287 par->CRTC[3] = ((htotal - 1) & 0x1F) | 0x80;
288 par->CRTC[4] = ((var->xres + var->right_margin) >> 3);
289 par->CRTC[5] = (((htotal - 1) & 0x20) << 2)
291 par->CRTC[6] = (vtotal - 2) & 0xFF;
292 par->CRTC[7] = (((vtotal - 2) & 0x100) >> 8)
299 par->CRTC[8] = 0x00;
300 par->CRTC[9] = (((var->yres - 1) & 0x200) >> 4) | 0x40;
303 par->CRTC[9] |= 0x80;
305 par->CRTC[10] = 0x00;
306 par->CRTC[11] = 0x00;
307 par->CRTC[12] = 0x00;
308 par->CRTC[13] = 0x00;
309 par->CRTC[14] = 0x00;
310 par->CRTC[15] = 0x00;
311 par->CRTC[16] = vsync_start & 0xFF;
312 par->CRTC[17] = (vsync_end & 0x0F) | 0x20;
313 par->CRTC[18] = (var->yres - 1) & 0xFF;
314 par->CRTC[19] = var->xres_virtual >> 4;
315 par->CRTC[20] = 0x00;
316 par->CRTC[21] = (var->yres - 1) & 0xFF;
317 par->CRTC[22] = (vtotal - 1) & 0xFF;
318 par->CRTC[23] = 0xC3;
319 par->CRTC[24] = 0xFF;
330 par->Graphics[0] = 0x00;
331 par->Graphics[1] = 0x00;
332 par->Graphics[2] = 0x00;
333 par->Graphics[3] = 0x00;
334 par->Graphics[4] = 0x00;
335 par->Graphics[5] = 0x40;
336 par->Graphics[6] = 0x05; /* only map 64k VGA memory !!!! */
337 par->Graphics[7] = 0x0F;
338 par->Graphics[8] = 0xFF;
341 par->Attribute[0] = 0x00; /* standard colormap translation */
342 par->Attribute[1] = 0x01;
343 par->Attribute[2] = 0x02;
344 par->Attribute[3] = 0x03;
345 par->Attribute[4] = 0x04;
346 par->Attribute[5] = 0x05;
347 par->Attribute[6] = 0x06;
348 par->Attribute[7] = 0x07;
349 par->Attribute[8] = 0x08;
350 par->Attribute[9] = 0x09;
351 par->Attribute[10] = 0x0A;
352 par->Attribute[11] = 0x0B;
353 par->Attribute[12] = 0x0C;
354 par->Attribute[13] = 0x0D;
355 par->Attribute[14] = 0x0E;
356 par->Attribute[15] = 0x0F;
357 par->Attribute[16] = 0x41;
358 par->Attribute[17] = 0xFF;
359 par->Attribute[18] = 0x0F;
360 par->Attribute[19] = 0x00;
361 par->Attribute[20] = 0x00;
444 const struct neofb_par *par)
448 vga_w(NULL, VGA_MIS_W, par->MiscOutReg);
451 vga_wseq(NULL, i, par->Sequencer[i]);
454 vga_wcrt(NULL, 17, par->CRTC[17] & ~0x80);
457 vga_wcrt(NULL, i, par->CRTC[i]);
460 vga_wgfx(NULL, i, par->Graphics[i]);
465 VGAwATTR(i, par->Attribute[i]);
478 struct neofb_par *par = info->par;
480 while (readl(&par->neo2200->bltStat) & 1)
517 struct neofb_par *par = info->par;
518 Neo2200 __iomem *neo2200 = par->neo2200;
552 struct neofb_par *par = info->par;
554 if (!par->ref_count) {
555 memset(&par->state, 0, sizeof(struct vgastate));
556 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
557 save_vga(&par->state);
559 par->ref_count++;
567 struct neofb_par *par = info->par;
569 if (!par->ref_count)
572 if (par->ref_count == 1) {
573 restore_vga(&par->state);
575 par->ref_count--;
583 struct neofb_par *par = info->par;
589 if (!var->pixclock || PICOS2KHZ(var->pixclock) > par->maxClock)
593 if (par->internal_display &&
594 ((var->xres > par->NeoPanelWidth) ||
595 (var->yres > par->NeoPanelHeight))) {
598 var->xres, var->yres, par->NeoPanelWidth,
599 par->NeoPanelHeight);
604 if (!par->internal_display)
617 if (var->yres == (par->libretto ? 480 : 600))
716 if (var->bits_per_pixel >= 24 || !par->neo2200)
723 struct neofb_par *par = info->par;
744 if (vgaHWInit(&info->var, par))
751 par->Attribute[16] = 0x01;
755 par->CRTC[0x13] = info->var.xres_virtual >> 3;
756 par->ExtCRTOffset = info->var.xres_virtual >> 11;
757 par->ExtColorModeSelect = 0x11;
760 par->CRTC[0x13] = info->var.xres_virtual >> 2;
761 par->ExtCRTOffset = info->var.xres_virtual >> 10;
762 par->ExtColorModeSelect = 0x13;
765 par->CRTC[0x13] = (info->var.xres_virtual * 3) >> 3;
766 par->ExtCRTOffset = (info->var.xres_virtual * 3) >> 11;
767 par->ExtColorModeSelect = 0x14;
771 par->CRTC[0x13] = info->var.xres_virtual >> 1;
772 par->ExtCRTOffset = info->var.xres_virtual >> 9;
773 par->ExtColorModeSelect = 0x15;
780 par->ExtCRTDispAddr = 0x10;
783 par->VerticalExt = (((vtotal - 2) & 0x400) >> 10)
789 if (par->pci_burst)
790 par->SysIfaceCntl1 = 0x30;
792 par->SysIfaceCntl1 = 0x00;
794 par->SysIfaceCntl2 = 0xc0; /* VESA Bios sets this to 0x80! */
797 par->PanelDispCntlRegRead = 1;
800 par->PanelDispCntlReg1 = 0x00;
801 if (par->internal_display)
802 par->PanelDispCntlReg1 |= 0x02;
803 if (par->external_display)
804 par->PanelDispCntlReg1 |= 0x01;
807 if (par->PanelDispCntlReg1 == 0x00) {
809 par->PanelDispCntlReg1 = vga_rgfx(NULL, 0x20) & 0x03;
815 par->PanelDispCntlReg1 |= 0x60;
818 par->PanelDispCntlReg1 |= 0x40;
821 par->PanelDispCntlReg1 |= 0x20;
829 switch (par->PanelDispCntlReg1 & 0x03) {
831 par->GeneralLockReg = 0x00;
833 par->ProgramVCLK = 1;
837 par->GeneralLockReg = 0x01;
839 par->ProgramVCLK = 0;
849 par->PanelDispCntlReg2 = 0x00;
850 par->PanelDispCntlReg3 = 0x00;
852 if (par->lcd_stretch && (par->PanelDispCntlReg1 == 0x02) && /* LCD only */
853 (info->var.xres != par->NeoPanelWidth)) {
861 par->PanelDispCntlReg2 |= 0xC6;
874 par->PanelVertCenterReg1 = 0x00;
875 par->PanelVertCenterReg2 = 0x00;
876 par->PanelVertCenterReg3 = 0x00;
877 par->PanelVertCenterReg4 = 0x00;
878 par->PanelVertCenterReg5 = 0x00;
879 par->PanelHorizCenterReg1 = 0x00;
880 par->PanelHorizCenterReg2 = 0x00;
881 par->PanelHorizCenterReg3 = 0x00;
882 par->PanelHorizCenterReg4 = 0x00;
883 par->PanelHorizCenterReg5 = 0x00;
886 if (par->PanelDispCntlReg1 & 0x02) {
887 if (info->var.xres == par->NeoPanelWidth) {
893 par->PanelDispCntlReg2 |= 0x01;
894 par->PanelDispCntlReg3 |= 0x10;
899 ((par->NeoPanelWidth -
902 ((par->NeoPanelHeight -
912 par->PanelHorizCenterReg3 = hoffset;
913 par->PanelVertCenterReg2 = voffset;
916 par->PanelHorizCenterReg4 = hoffset;
917 par->PanelVertCenterReg1 = voffset;
920 par->PanelHorizCenterReg1 = hoffset;
921 par->PanelVertCenterReg3 = voffset;
924 par->PanelHorizCenterReg2 = hoffset;
925 par->PanelVertCenterReg4 = voffset;
928 par->PanelHorizCenterReg5 = hoffset;
929 par->PanelVertCenterReg5 = voffset;
939 par->biosMode =
947 neoCalcVCLK(info, par, PICOS2KHZ(info->var.pixclock));
950 par->MiscOutReg |= 0x0C;
959 vga_wgfx(NULL, 0x0A, par->GeneralLockReg);
972 temp |= (par->ExtColorModeSelect & ~0xF0);
983 temp |= (par->ExtColorModeSelect & ~0x70);
1011 vgaHWRestore(info, par);
1048 vga_wgfx(NULL, 0x0E, par->ExtCRTDispAddr);
1049 vga_wgfx(NULL, 0x0F, par->ExtCRTOffset);
1052 temp |= (par->SysIfaceCntl1 & ~0x0F); /* VESA Bios sets bit 1! */
1055 vga_wgfx(NULL, 0x11, par->SysIfaceCntl2);
1056 vga_wgfx(NULL, 0x15, 0 /*par->SingleAddrPage */ );
1057 vga_wgfx(NULL, 0x16, 0 /*par->DualAddrPage */ );
1063 temp |= (par->PanelDispCntlReg1 & ~0xFC);
1070 temp |= (par->PanelDispCntlReg1 & ~0xDC);
1077 temp |= (par->PanelDispCntlReg1 & ~0x98);
1084 temp |= (par->PanelDispCntlReg2 & ~0x38);
1090 temp |= (par->PanelDispCntlReg3 & ~0xEF);
1094 vga_wgfx(NULL, 0x28, par->PanelVertCenterReg1);
1095 vga_wgfx(NULL, 0x29, par->PanelVertCenterReg2);
1096 vga_wgfx(NULL, 0x2a, par->PanelVertCenterReg3);
1099 vga_wgfx(NULL, 0x32, par->PanelVertCenterReg4);
1100 vga_wgfx(NULL, 0x33, par->PanelHorizCenterReg1);
1101 vga_wgfx(NULL, 0x34, par->PanelHorizCenterReg2);
1102 vga_wgfx(NULL, 0x35, par->PanelHorizCenterReg3);
1106 vga_wgfx(NULL, 0x36, par->PanelHorizCenterReg4);
1112 vga_wgfx(NULL, 0x36, par->PanelHorizCenterReg4);
1113 vga_wgfx(NULL, 0x37, par->PanelVertCenterReg5);
1114 vga_wgfx(NULL, 0x38, par->PanelHorizCenterReg5);
1120 if (par->ProgramVCLK && ((vga_rgfx(NULL, 0x9B) != par->VCLK3NumeratorLow)
1121 || (vga_rgfx(NULL, 0x9F) != par->VCLK3Denominator)
1123 != (par->VCLK3NumeratorHigh &
1125 vga_wgfx(NULL, 0x9B, par->VCLK3NumeratorLow);
1129 temp |= (par->VCLK3NumeratorHigh & ~0x0F);
1132 vga_wgfx(NULL, 0x9F, par->VCLK3Denominator);
1135 if (par->biosMode)
1136 vga_wcrt(NULL, 0x23, par->biosMode);
1145 vga_wcrt(NULL, 0x70, par->VerticalExt);
1151 neoLock(&par->state);
1175 struct neofb_par *par = info->par;
1176 struct vgastate *state = &par->state;
1264 struct neofb_par *par = info->par;
1273 neoLock(&par->state);
1279 if (par->PanelDispCntlRegRead) {
1280 par->PanelDispCntlReg1 = tmpdisp;
1282 par->PanelDispCntlRegRead = !blank_mode;
1324 lcdflags = ((par->PanelDispCntlReg1 | tmpdisp) & 0x02); /* LCD normal */
1329 lcdflags = ((par->PanelDispCntlReg1 | tmpdisp) & 0x02); /* LCD normal */
1356 neoLock(&par->state);
1363 struct neofb_par *par = info->par;
1376 rop, &par->neo2200->bltCntl);
1380 writel(rect->color, &par->neo2200->fgColor);
1385 &par->neo2200->fgColor);
1390 &par->neo2200->dstStart);
1392 &par->neo2200->xyExt);
1399 struct neofb_par *par = info->par;
1420 writel(bltCntl, &par->neo2200->bltCntl);
1422 writel(src, &par->neo2200->srcStart);
1423 writel(dst, &par->neo2200->dstStart);
1425 &par->neo2200->xyExt);
1431 struct neofb_par *par = info->par;
1465 writel(image->fg_color, &par->neo2200->fgColor);
1466 writel(image->bg_color, &par->neo2200->bgColor);
1471 &par->neo2200->fgColor);
1473 &par->neo2200->bgColor);
1480 0x0c0000, &par->neo2200->bltCntl);
1482 writel(0, &par->neo2200->srcStart);
1483 // par->neo2200->dstStart = (image->dy << 16) | (image->dx & 0xffff);
1485 image->dy * info->fix.line_length), &par->neo2200->dstStart);
1487 &par->neo2200->xyExt);
1489 memcpy_toio(par->mmio_vbase + 0x100000, image->data, data_len);
1566 struct neofb_par *par = (struct neofb_par *) info->par;
1569 write_le32(NEOREG_CURSCNTL, ~NEO_CURS_ENABLE, par);
1577 write_le32(NEOREG_CURSX, x, par);
1578 write_le32(NEOREG_CURSY, y, par);
1599 write_le32(NEOREG_CURSFGCOLOR, fg, par);
1600 write_le32(NEOREG_CURSBGCOLOR, bg, par);
1608 write_le32(NEOREG_CURSCNTL, NEO_CURS_ENABLE, par);
1646 struct neofb_par *par = info->par;
1679 par->mmio_vbase = ioremap(info->fix.mmio_start, MMIO_SIZE);
1680 if (!par->mmio_vbase) {
1687 par->mmio_vbase);
1693 struct neofb_par *par = info->par;
1697 iounmap(par->mmio_vbase);
1698 par->mmio_vbase = NULL;
1708 struct neofb_par *par = info->par;
1732 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
1742 ((0x0ff0 & (addr >> 10)) >> 4), par);
1750 struct neofb_par *par = info->par;
1754 arch_phys_wc_del(par->wc_cookie);
1764 struct neofb_par *par = info->par;
1778 if (!par->internal_display && !par->external_display) {
1779 par->internal_display = display & 2 || !(display & 3) ? 1 : 0;
1780 par->external_display = display & 1;
1782 par->internal_display && par->external_display ? "simultaneous" :
1783 par->internal_display ? "internal" : "external");
1792 par->NeoPanelWidth = 640;
1793 par->NeoPanelHeight = 480;
1797 par->NeoPanelWidth = 800;
1798 if (par->libretto) {
1799 par->NeoPanelHeight = 480;
1803 par->NeoPanelHeight = 600;
1809 par->NeoPanelWidth = 1024;
1810 par->NeoPanelHeight = 768;
1816 par->NeoPanelWidth = 1280;
1817 par->NeoPanelHeight = 1024;
1828 par->NeoPanelWidth = 640;
1829 par->NeoPanelHeight = 480;
1835 par->NeoPanelWidth,
1836 par->NeoPanelHeight,
1844 struct neofb_par *par = info->par;
1910 par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
1920 par->maxClock = maxClock;
1921 par->cursorOff = CursorOff;
1930 struct neofb_par *par;
1937 par = info->par;
1941 par->pci_burst = !nopciburst;
1942 par->lcd_stretch = !nostretch;
1943 par->libretto = libretto;
1945 par->internal_display = internal;
1946 par->external_display = external;
1999 info->pseudo_palette = par->palette;