Lines Matching defs:par
84 struct mb862xxfb_par *par = info->par;
93 par->pseudo_palette[regno] = val;
206 struct mb862xxfb_par *par = fbi->par;
209 dev_dbg(par->dev, "%s\n", __func__);
210 if (par->type == BT_CORALP)
213 if (par->pre_init)
222 sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
227 dev_dbg(par->dev, "SC 0x%lx\n", sc);
276 struct mb862xxfb_par *par = info->par;
289 struct mb862xxfb_par *par = fbi->par;
317 struct mb862xxfb_par *par = fbi->par;
318 struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg;
368 outreg(disp, GC_L1DA, par->cap_buf);
374 (par->l1_stride << 16));
422 struct mb862xxfb_par *par = fbi->par;
423 struct mb862xx_gc_mode *mode = par->gc_mode;
428 fbi->pseudo_palette = par->pseudo_palette;
429 fbi->screen_base = par->fb_base;
430 fbi->screen_size = par->mapped_vram;
433 fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
434 fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
435 fbi->fix.mmio_len = par->mmio_len;
449 dev_dbg(par->dev, "using bootloader's disp. mode\n");
450 fbi->var.pixclock = (sc * 1000000) / par->refclk;
478 dev_dbg(par->dev, "using supplied mode\n");
487 dev_err(par->dev,
511 dev_err(par->dev, "check_var() failed on initial setup?\n");
523 par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000;
524 par->cap_len = 0x1bd800;
525 par->l1_cfg.sx = 0;
526 par->l1_cfg.sy = 0;
527 par->l1_cfg.sw = 720;
528 par->l1_cfg.sh = 576;
529 par->l1_cfg.dx = 0;
530 par->l1_cfg.dy = 0;
531 par->l1_cfg.dw = 720;
532 par->l1_cfg.dh = 576;
533 stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8);
534 par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0);
536 (par->l1_stride << 16));
537 outreg(cap, GC_CAP_CBOA, par->cap_buf);
538 outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len);
549 struct mb862xxfb_par *par = fbi->par;
584 struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
587 if (!par)
590 if (par->type == BT_CARMINE) {
622 static int mb862xx_gdc_init(struct mb862xxfb_par *par)
627 if (!par)
631 par->pre_init = 1;
633 par->host = par->mmio_base;
634 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
635 par->disp = par->mmio_base + MB862XX_DISP_BASE;
636 par->cap = par->mmio_base + MB862XX_CAP_BASE;
637 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
638 par->geo = par->mmio_base + MB862XX_GEO_BASE;
639 par->pio = par->mmio_base + MB862XX_PIO_BASE;
641 par->refclk = GC_DISP_REFCLK_400;
646 dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
648 par->type = BT_LIME;
649 ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
650 mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
652 dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
656 if (!par->pre_init) {
673 struct mb862xxfb_par *par;
688 par = info->par;
689 par->info = info;
690 par->dev = dev;
692 par->irq = irq_of_parse_and_map(np, 0);
693 if (!par->irq) {
700 par->res = request_mem_region(res.start, res_size, DRV_NAME);
701 if (par->res == NULL) {
708 par->gc_mode = &socrates_gc_mode;
711 par->fb_base_phys = res.start;
712 par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
713 par->mmio_len = MB862XX_MMIO_SIZE;
714 if (par->gc_mode)
715 par->mapped_vram = par->gc_mode->max_vram;
717 par->mapped_vram = MB862XX_MEM_SIZE;
719 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
720 if (par->fb_base == NULL) {
725 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
726 if (par->mmio_base == NULL) {
732 (u64)par->fb_base_phys, (ulong)par->mapped_vram);
734 (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
736 if (mb862xx_gdc_init(par))
739 if (request_irq(par->irq, mb862xx_intr, 0,
740 DRV_NAME, (void *)par)) {
770 free_irq(par->irq, (void *)par);
772 iounmap(par->mmio_base);
774 iounmap(par->fb_base);
778 irq_dispose_mapping(par->irq);
787 struct mb862xxfb_par *par = fbi->par;
788 resource_size_t res_size = resource_size(par->res);
801 free_irq(par->irq, (void *)par);
802 irq_dispose_mapping(par->irq);
809 iounmap(par->mmio_base);
810 iounmap(par->fb_base);
812 release_mem_region(par->res->start, res_size);
842 static int coralp_init(struct mb862xxfb_par *par)
846 par->host = par->mmio_base;
847 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
848 par->disp = par->mmio_base + MB862XX_DISP_BASE;
849 par->cap = par->mmio_base + MB862XX_CAP_BASE;
850 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
851 par->geo = par->mmio_base + MB862XX_GEO_BASE;
852 par->pio = par->mmio_base + MB862XX_PIO_BASE;
854 par->refclk = GC_DISP_REFCLK_400;
856 if (par->mapped_vram >= 0x2000000) {
858 writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
868 dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
870 par->pdev->revision);
873 par->pre_init = 1;
875 if (!par->pre_init) {
887 mb862xx_i2c_init(par);
891 static int init_dram_ctrl(struct mb862xxfb_par *par)
914 dev_err(par->dev, "VRAM init failed.\n");
923 static int carmine_init(struct mb862xxfb_par *par)
927 par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
928 par->i2c = par->mmio_base + MB86297_I2C_BASE;
929 par->disp = par->mmio_base + MB86297_DISP0_BASE;
930 par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
931 par->cap = par->mmio_base + MB86297_CAP0_BASE;
932 par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
933 par->draw = par->mmio_base + MB86297_DRAW_BASE;
934 par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
935 par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
937 par->refclk = GC_DISP_REFCLK_533;
945 dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
946 par->pdev->revision);
954 if (init_dram_ctrl(par) < 0)
965 static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
967 switch (par->type) {
969 return coralp_init(par);
971 return carmine_init(par);
994 struct mb862xxfb_par *par;
1015 par = info->par;
1016 par->info = info;
1017 par->dev = dev;
1018 par->pdev = pdev;
1019 par->irq = pdev->irq;
1030 par->fb_base_phys = pci_resource_start(par->pdev, 0);
1031 par->mapped_vram = CORALP_MEM_SIZE;
1032 if (par->mapped_vram >= 0x2000000) {
1033 par->mmio_base_phys = par->fb_base_phys +
1036 par->mmio_base_phys = par->fb_base_phys +
1039 par->mmio_len = MB862XX_MMIO_SIZE;
1040 par->type = BT_CORALP;
1043 par->fb_base_phys = pci_resource_start(par->pdev, 2);
1044 par->mmio_base_phys = pci_resource_start(par->pdev, 3);
1045 par->mmio_len = pci_resource_len(par->pdev, 3);
1046 par->mapped_vram = CARMINE_MEM_SIZE;
1047 par->type = BT_CARMINE;
1055 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
1056 if (par->fb_base == NULL) {
1062 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
1063 if (par->mmio_base == NULL) {
1070 (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
1072 (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
1074 ret = mb862xx_pci_gdc_init(par);
1078 ret = request_irq(par->irq, mb862xx_intr, IRQF_SHARED,
1079 DRV_NAME, (void *)par);
1107 if (par->type == BT_CARMINE)
1117 free_irq(par->irq, (void *)par);
1119 iounmap(par->mmio_base);
1121 iounmap(par->fb_base);
1135 struct mb862xxfb_par *par = fbi->par;
1145 if (par->type == BT_CARMINE) {
1152 mb862xx_i2c_exit(par);
1159 free_irq(par->irq, (void *)par);
1160 iounmap(par->mmio_base);
1161 iounmap(par->fb_base);