Lines Matching refs:m2
664 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2,
670 m = (5 * (m1 + 2)) + (m2 + 2);
714 int i, m1, m2, n, p1, p2;
727 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
731 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
732 m1, m2, n, p1, p2);
734 calc_vclock(index, m1, m2, n, p1, p2, 0));
738 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
741 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
742 m1, m2, n, p1, p2);
744 calc_vclock(index, m1, m2, n, p1, p2, 0));
755 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
759 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
760 m1, m2, n, p1, p2);
762 calc_vclock(index, m1, m2, n, p1, p2, 0));
766 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
770 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
771 m1, m2, n, p1, p2);
773 calc_vclock(index, m1, m2, n, p1, p2, 0));
881 int m1, m2;
887 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
888 testm = (5 * (m1 + 2)) + (m2 + 2);
891 *retm2 = (unsigned int)m2;
938 u32 m1, m2, n, p1, p2, n1, testm;
977 if (splitm(index, testm, &m1, &m2)) {
1006 splitm(index, m, &m1, &m2);
1012 m, m1, m2, n, n1, p, p1, p2,
1014 calc_vclock(index, m1, m2, n1, p1, p2, 0),
1017 *retm2 = m2;
1021 *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
1044 u32 m1, m2, n, p1, p2, clock_target, clock;
1113 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1126 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1143 (m2 << FP_M2_DIVISOR_SHIFT);