Lines Matching refs:dinfo
67 int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
70 if (!pdev || !dinfo)
75 dinfo->name = "Intel(R) 830M";
76 dinfo->chipset = INTEL_830M;
77 dinfo->mobile = 1;
78 dinfo->pll_index = PLLS_I8xx;
81 dinfo->name = "Intel(R) 845G";
82 dinfo->chipset = INTEL_845G;
83 dinfo->mobile = 0;
84 dinfo->pll_index = PLLS_I8xx;
87 dinfo->mobile = 1;
88 dinfo->name = "Intel(R) 854";
89 dinfo->chipset = INTEL_854;
93 dinfo->mobile = 1;
94 dinfo->pll_index = PLLS_I8xx;
99 dinfo->name = "Intel(R) 855GME";
100 dinfo->chipset = INTEL_855GME;
103 dinfo->name = "Intel(R) 855GM";
104 dinfo->chipset = INTEL_855GM;
107 dinfo->name = "Intel(R) 852GME";
108 dinfo->chipset = INTEL_852GME;
111 dinfo->name = "Intel(R) 852GM";
112 dinfo->chipset = INTEL_852GM;
115 dinfo->name = "Intel(R) 852GM/855GM";
116 dinfo->chipset = INTEL_85XGM;
121 dinfo->name = "Intel(R) 865G";
122 dinfo->chipset = INTEL_865G;
123 dinfo->mobile = 0;
124 dinfo->pll_index = PLLS_I8xx;
127 dinfo->name = "Intel(R) 915G";
128 dinfo->chipset = INTEL_915G;
129 dinfo->mobile = 0;
130 dinfo->pll_index = PLLS_I9xx;
133 dinfo->name = "Intel(R) 915GM";
134 dinfo->chipset = INTEL_915GM;
135 dinfo->mobile = 1;
136 dinfo->pll_index = PLLS_I9xx;
139 dinfo->name = "Intel(R) 945G";
140 dinfo->chipset = INTEL_945G;
141 dinfo->mobile = 0;
142 dinfo->pll_index = PLLS_I9xx;
145 dinfo->name = "Intel(R) 945GM";
146 dinfo->chipset = INTEL_945GM;
147 dinfo->mobile = 1;
148 dinfo->pll_index = PLLS_I9xx;
151 dinfo->name = "Intel(R) 945GME";
152 dinfo->chipset = INTEL_945GME;
153 dinfo->mobile = 1;
154 dinfo->pll_index = PLLS_I9xx;
157 dinfo->name = "Intel(R) 965G";
158 dinfo->chipset = INTEL_965G;
159 dinfo->mobile = 0;
160 dinfo->pll_index = PLLS_I9xx;
163 dinfo->name = "Intel(R) 965GM";
164 dinfo->chipset = INTEL_965GM;
165 dinfo->mobile = 1;
166 dinfo->pll_index = PLLS_I9xx;
280 int intelfbhw_check_non_crt(struct intelfb_info *dinfo)
311 int intelfbhw_validate_mode(struct intelfb_info *dinfo,
327 if (tmp > dinfo->fb.size) {
330 BtoKB(tmp), BtoKB(dinfo->fb.size));
383 struct intelfb_info *dinfo = GET_DINFO(info);
397 offset = (yoffset * dinfo->pitch) +
400 offset += dinfo->fb.offset << 12;
402 dinfo->vsync.pan_offset = offset;
404 !intelfbhw_enable_irq(dinfo))
405 dinfo->vsync.pan_display = 1;
407 dinfo->vsync.pan_display = 0;
417 struct intelfb_info *dinfo = GET_DINFO(info);
437 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
439 if (dinfo->cursor_on) {
441 intelfbhw_cursor_hide(dinfo);
443 intelfbhw_cursor_show(dinfo);
444 dinfo->cursor_on = 1;
446 dinfo->cursor_blanked = blank;
497 void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
501 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
516 int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
525 if (!hw || !dinfo)
682 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll,
687 if (IS_I9XX(dinfo)) {
710 void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
715 int index = dinfo->pll_index;
729 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
740 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
757 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
768 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
1038 int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
1113 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1135 if (IS_I9XX(dinfo)) {
1246 hw->disp_a_stride = dinfo->pitch;
1252 hw->disp_a_base += dinfo->fb.offset << 12;
1255 stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1275 int intelfbhw_program_mode(struct intelfb_info *dinfo,
1298 dinfo->pipe = intelfbhw_active_pipe(hw);
1300 if (dinfo->pipe == PIPE_B) {
1427 switch (dinfo->info->var.vmode & (FB_VMODE_INTERLACED |
1448 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1480 static void refresh_ring(struct intelfb_info *dinfo);
1481 static void reset_state(struct intelfb_info *dinfo);
1482 static void do_flush(struct intelfb_info *dinfo);
1484 static u32 get_ring_space(struct intelfb_info *dinfo)
1488 if (dinfo->ring_tail >= dinfo->ring_head)
1489 ring_space = dinfo->ring.size -
1490 (dinfo->ring_tail - dinfo->ring_head);
1492 ring_space = dinfo->ring_head - dinfo->ring_tail;
1502 static int wait_ring(struct intelfb_info *dinfo, int n)
1513 while (dinfo->ring_space < n) {
1514 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1515 dinfo->ring_space = get_ring_space(dinfo);
1517 if (dinfo->ring_head != last_head) {
1519 last_head = dinfo->ring_head;
1525 reset_state(dinfo);
1526 refresh_ring(dinfo);
1527 do_flush(dinfo);
1532 dinfo->ring_space, n);
1535 dinfo->ring_lockup = 1;
1544 static void do_flush(struct intelfb_info *dinfo)
1552 void intelfbhw_do_sync(struct intelfb_info *dinfo)
1558 if (!dinfo->accel)
1566 do_flush(dinfo);
1567 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1568 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1571 static void refresh_ring(struct intelfb_info *dinfo)
1577 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1578 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1579 dinfo->ring_space = get_ring_space(dinfo);
1582 static void reset_state(struct intelfb_info *dinfo)
1600 refresh_ring(dinfo);
1601 intelfbhw_do_sync(dinfo);
1612 void intelfbhw_2d_stop(struct intelfb_info *dinfo)
1616 dinfo->accel, dinfo->ring_active);
1619 if (!dinfo->accel)
1622 dinfo->ring_active = 0;
1623 reset_state(dinfo);
1631 void intelfbhw_2d_start(struct intelfb_info *dinfo)
1635 dinfo->accel, dinfo->ring_active);
1638 if (!dinfo->accel)
1646 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1648 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1650 refresh_ring(dinfo);
1651 dinfo->ring_active = 1;
1655 void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w,
1666 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1694 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1695 dinfo->ring_tail, dinfo->ring_space);
1700 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1711 br09 = dinfo->fb_start;
1713 br12 = dinfo->fb_start;
1745 int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1782 br09 = dinfo->fb_start;
1834 void intelfbhw_cursor_init(struct intelfb_info *dinfo)
1842 if (dinfo->mobile || IS_I9XX(dinfo)) {
1843 if (!dinfo->cursor.physical)
1851 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1858 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1865 void intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1873 dinfo->cursor_on = 0;
1874 if (dinfo->mobile || IS_I9XX(dinfo)) {
1875 if (!dinfo->cursor.physical)
1882 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1890 void intelfbhw_cursor_show(struct intelfb_info *dinfo)
1898 dinfo->cursor_on = 1;
1900 if (dinfo->cursor_blanked)
1903 if (dinfo->mobile || IS_I9XX(dinfo)) {
1904 if (!dinfo->cursor.physical)
1911 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1919 void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1937 if (IS_I9XX(dinfo))
1938 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1941 void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1953 void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1956 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1964 if (!dinfo->cursor.virtual)
1982 void intelfbhw_cursor_reset(struct intelfb_info *dinfo)
1984 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1991 if (!dinfo->cursor.virtual)
2006 struct intelfb_info *dinfo = dev_id;
2008 spin_lock(&dinfo->int_lock);
2011 if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
2017 spin_unlock(&dinfo->int_lock);
2025 if (dinfo->vsync.pan_display) {
2026 dinfo->vsync.pan_display = 0;
2027 OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2030 dinfo->vsync.count++;
2031 wake_up_interruptible(&dinfo->vsync.wait);
2033 spin_unlock(&dinfo->int_lock);
2038 int intelfbhw_enable_irq(struct intelfb_info *dinfo)
2041 if (!test_and_set_bit(0, &dinfo->irq_flags)) {
2042 if (request_irq(dinfo->pdev->irq, intelfbhw_irq, IRQF_SHARED,
2043 "intelfb", dinfo)) {
2044 clear_bit(0, &dinfo->irq_flags);
2048 spin_lock_irq(&dinfo->int_lock);
2052 spin_lock_irq(&dinfo->int_lock);
2054 if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
2063 spin_unlock_irq(&dinfo->int_lock);
2067 void intelfbhw_disable_irq(struct intelfb_info *dinfo)
2069 if (test_and_clear_bit(0, &dinfo->irq_flags)) {
2070 if (dinfo->vsync.pan_display) {
2071 dinfo->vsync.pan_display = 0;
2072 OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2074 spin_lock_irq(&dinfo->int_lock);
2080 spin_unlock_irq(&dinfo->int_lock);
2082 free_irq(dinfo->pdev->irq, dinfo);
2086 int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe)
2094 vsync = &dinfo->vsync;
2100 ret = intelfbhw_enable_irq(dinfo);