Lines Matching refs:par
96 static inline void i740outb(struct i740fb_par *par, u16 port, u8 val)
98 vga_mm_w(par->regs, port, val);
100 static inline u8 i740inb(struct i740fb_par *par, u16 port)
102 return vga_mm_r(par->regs, port);
104 static inline void i740outreg(struct i740fb_par *par, u16 port, u8 reg, u8 val)
106 vga_mm_w_fast(par->regs, port, reg, val);
108 static inline u8 i740inreg(struct i740fb_par *par, u16 port, u8 reg)
110 vga_mm_w(par->regs, port, reg);
111 return vga_mm_r(par->regs, port+1);
113 static inline void i740outreg_mask(struct i740fb_par *par, u16 port, u8 reg,
116 vga_mm_w_fast(par->regs, port, reg, (val & mask)
117 | (i740inreg(par, port, reg) & ~mask));
127 struct i740fb_par *par = data;
129 i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SCL, DDC_SCL);
130 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL);
135 struct i740fb_par *par = data;
137 i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SDA, DDC_SDA);
138 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA);
143 struct i740fb_par *par = data;
145 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL);
147 return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SCL);
152 struct i740fb_par *par = data;
154 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA);
156 return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SDA);
161 struct i740fb_par *par = info->par;
163 strscpy(par->ddc_adapter.name, info->fix.id,
164 sizeof(par->ddc_adapter.name));
165 par->ddc_adapter.owner = THIS_MODULE;
166 par->ddc_adapter.class = I2C_CLASS_DDC;
167 par->ddc_adapter.algo_data = &par->ddc_algo;
168 par->ddc_adapter.dev.parent = info->device;
169 par->ddc_algo.setsda = i740fb_ddc_setsda;
170 par->ddc_algo.setscl = i740fb_ddc_setscl;
171 par->ddc_algo.getsda = i740fb_ddc_getsda;
172 par->ddc_algo.getscl = i740fb_ddc_getscl;
173 par->ddc_algo.udelay = 10;
174 par->ddc_algo.timeout = 20;
175 par->ddc_algo.data = par;
177 i2c_set_adapdata(&par->ddc_adapter, par);
179 return i2c_bit_add_bus(&par->ddc_adapter);
184 struct i740fb_par *par = info->par;
186 mutex_lock(&(par->open_lock));
187 par->ref_count++;
188 mutex_unlock(&(par->open_lock));
195 struct i740fb_par *par = info->par;
197 mutex_lock(&(par->open_lock));
198 if (par->ref_count == 0) {
200 mutex_unlock(&(par->open_lock));
204 par->ref_count--;
205 mutex_unlock(&(par->open_lock));
210 static u32 i740_calc_fifo(struct i740fb_par *par, u32 freq, int bpp)
235 if (par->has_sgram) {
272 if (par->has_sgram) {
307 if (par->has_sgram) {
345 static void i740_calc_vclk(u32 freq, struct i740fb_par *par)
386 par->video_clk2_m = (m_best - 2) & 0xFF;
387 par->video_clk2_n = (n_best - 2) & 0xFF;
388 par->video_clk2_mn_msbs = ((((n_best - 2) >> 4) & VCO_N_MSBS)
390 par->video_clk2_div_sel = ((p_best << 4) | REF_DIV_1);
394 struct i740fb_par *par, struct fb_info *info)
444 dacspeed24 = par->has_sgram ? DACSPEED24_SG : DACSPEED24_SD;
502 par->crtc[VGA_CRTC_H_TOTAL] = (xtotal >> 3) - 5;
503 par->crtc[VGA_CRTC_H_DISP] = (xres >> 3) - 1;
504 par->crtc[VGA_CRTC_H_BLANK_START] = ((xres + right) >> 3) - 1;
505 par->crtc[VGA_CRTC_H_SYNC_START] = (xres + right) >> 3;
506 par->crtc[VGA_CRTC_H_SYNC_END] = (((xres + right + hslen) >> 3) & 0x1F)
508 par->crtc[VGA_CRTC_H_BLANK_END] = ((xres + right + hslen) >> 3 & 0x1F)
511 par->crtc[VGA_CRTC_V_TOTAL] = ytotal - 2;
519 par->crtc[VGA_CRTC_PRESET_ROW] = 0;
520 par->crtc[VGA_CRTC_MAX_SCAN] = 0x40; /* 1 scanline, no linecmp */
522 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x80;
523 par->crtc[VGA_CRTC_CURSOR_START] = 0x00;
524 par->crtc[VGA_CRTC_CURSOR_END] = 0x00;
525 par->crtc[VGA_CRTC_CURSOR_HI] = 0x00;
526 par->crtc[VGA_CRTC_CURSOR_LO] = 0x00;
527 par->crtc[VGA_CRTC_V_DISP_END] = yres-1;
533 par->crtc[VGA_CRTC_V_BLANK_START] = yres + lower - 1;
534 par->crtc[VGA_CRTC_V_SYNC_START] = yres + lower - 1;
538 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x20;
543 par->crtc[VGA_CRTC_V_SYNC_END] =
546 par->crtc[VGA_CRTC_V_BLANK_END] = (yres + lower - 1 + vslen) & 0xFF;
548 par->crtc[VGA_CRTC_UNDERLINE] = 0x00;
549 par->crtc[VGA_CRTC_MODE] = 0xC3 ;
550 par->crtc[VGA_CRTC_LINE_COMPARE] = 0xFF;
551 par->crtc[VGA_CRTC_OVERFLOW] = r7;
553 par->vss = 0x00; /* 3DA */
556 par->atc[i] = i;
557 par->atc[VGA_ATC_MODE] = 0x81;
558 par->atc[VGA_ATC_OVERSCAN] = 0x00; /* 0 for EGA, 0xFF for VGA */
559 par->atc[VGA_ATC_PLANE_ENABLE] = 0x0F;
560 par->atc[VGA_ATC_COLOR_PAGE] = 0x00;
562 par->misc = 0xC3;
564 par->misc &= ~0x40;
566 par->misc &= ~0x80;
568 par->seq[VGA_SEQ_CLOCK_MODE] = 0x01;
569 par->seq[VGA_SEQ_PLANE_WRITE] = 0x0F;
570 par->seq[VGA_SEQ_CHARACTER_MAP] = 0x00;
571 par->seq[VGA_SEQ_MEMORY_MODE] = 0x06;
573 par->gdc[VGA_GFX_SR_VALUE] = 0x00;
574 par->gdc[VGA_GFX_SR_ENABLE] = 0x00;
575 par->gdc[VGA_GFX_COMPARE_VALUE] = 0x00;
576 par->gdc[VGA_GFX_DATA_ROTATE] = 0x00;
577 par->gdc[VGA_GFX_PLANE_READ] = 0;
578 par->gdc[VGA_GFX_MODE] = 0x02;
579 par->gdc[VGA_GFX_MISC] = 0x05;
580 par->gdc[VGA_GFX_COMPARE_MASK] = 0x0F;
581 par->gdc[VGA_GFX_BIT_MASK] = 0xFF;
586 par->crtc[VGA_CRTC_OFFSET] = vxres >> 3;
587 par->ext_offset = vxres >> 11;
588 par->pixelpipe_cfg1 = DISPLAY_8BPP_MODE;
589 par->bitblt_cntl = COLEXP_8BPP;
593 par->pixelpipe_cfg1 = (var->green.length == 6) ?
595 par->crtc[VGA_CRTC_OFFSET] = vxres >> 2;
596 par->ext_offset = vxres >> 10;
597 par->bitblt_cntl = COLEXP_16BPP;
601 par->crtc[VGA_CRTC_OFFSET] = (vxres * 3) >> 3;
602 par->ext_offset = (vxres * 3) >> 11;
603 par->pixelpipe_cfg1 = DISPLAY_24BPP_MODE;
604 par->bitblt_cntl = COLEXP_24BPP;
609 par->crtc[VGA_CRTC_OFFSET] = vxres >> 1;
610 par->ext_offset = vxres >> 9;
611 par->pixelpipe_cfg1 = DISPLAY_32BPP_MODE;
612 par->bitblt_cntl = COLEXP_RESERVED; /* Unimplemented on i740 */
617 par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
618 par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8;
619 par->ext_start_addr =
621 par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
623 par->pixelpipe_cfg0 = DAC_8_BIT;
625 par->pixelpipe_cfg2 = DISPLAY_GAMMA_ENABLE | OVERLAY_GAMMA_ENABLE;
626 par->io_cntl = EXTENDED_CRTC_CNTL;
627 par->address_mapping = LINEAR_MODE_ENABLE | PAGE_MAPPING_ENABLE;
628 par->display_cntl = HIRES_MODE;
631 par->pll_cntl = PLL_MEMCLK_100000KHZ; /* 100 MHz -- use as default */
634 par->ext_vert_total = (ytotal - 2) >> 8;
635 par->ext_vert_disp_end = (yres - 1) >> 8;
636 par->ext_vert_sync_start = (yres + lower) >> 8;
637 par->ext_vert_blank_start = (yres + lower) >> 8;
638 par->ext_horiz_total = ((xtotal >> 3) - 5) >> 8;
639 par->ext_horiz_blank = (((xres + right) >> 3) & 0x40) >> 6;
641 par->interlace_cntl = INTERLACE_DISABLE;
644 par->atc[VGA_ATC_OVERSCAN] = 0;
652 i740_calc_vclk(freq, par);
655 par->misc |= 0x0C;
658 par->lmi_fifo_watermark =
659 i740_calc_fifo(par, 1000000 / var->pixclock, bpp);
724 static void vga_protect(struct i740fb_par *par)
727 i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0x20, 0x20);
729 i740inb(par, 0x3DA);
730 i740outb(par, VGA_ATT_W, 0x00); /* enable palette access */
733 static void vga_unprotect(struct i740fb_par *par)
736 i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0, 0x20);
738 i740inb(par, 0x3DA);
739 i740outb(par, VGA_ATT_W, 0x20); /* disable palette access */
744 struct i740fb_par *par = info->par;
748 i = i740fb_decode_var(&info->var, par, info);
754 vga_protect(par);
756 i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_DISABLE);
760 i740outreg(par, XRX, VCLK2_VCO_M, par->video_clk2_m);
761 i740outreg(par, XRX, VCLK2_VCO_N, par->video_clk2_n);
762 i740outreg(par, XRX, VCLK2_VCO_MN_MSBS, par->video_clk2_mn_msbs);
763 i740outreg(par, XRX, VCLK2_VCO_DIV_SEL, par->video_clk2_div_sel);
765 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0,
766 par->pixelpipe_cfg0 & DAC_8_BIT, 0x80);
768 i740inb(par, 0x3DA);
769 i740outb(par, 0x3C0, 0x00);
772 i740outb(par, VGA_MIS_W, par->misc | 0x01);
775 i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x01);
777 i740outreg(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE,
778 par->seq[VGA_SEQ_CLOCK_MODE] | 0x20);
780 i740outreg(par, VGA_SEQ_I, i, par->seq[i]);
783 i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x03);
786 i740outreg(par, VGA_CRT_IC, VGA_CRTC_V_SYNC_END,
787 par->crtc[VGA_CRTC_V_SYNC_END]);
791 i740outreg(par, VGA_CRT_IC, i, par->crtc[i]);
795 i740outreg(par, VGA_GFX_I, i, par->gdc[i]);
799 i740inb(par, VGA_IS1_RC); /* reset flip-flop */
800 i740outb(par, VGA_ATT_IW, i);
801 i740outb(par, VGA_ATT_IW, par->atc[i]);
804 i740inb(par, VGA_IS1_RC);
805 i740outb(par, VGA_ATT_IW, 0x20);
807 i740outreg(par, VGA_CRT_IC, EXT_VERT_TOTAL, par->ext_vert_total);
808 i740outreg(par, VGA_CRT_IC, EXT_VERT_DISPLAY, par->ext_vert_disp_end);
809 i740outreg(par, VGA_CRT_IC, EXT_VERT_SYNC_START,
810 par->ext_vert_sync_start);
811 i740outreg(par, VGA_CRT_IC, EXT_VERT_BLANK_START,
812 par->ext_vert_blank_start);
813 i740outreg(par, VGA_CRT_IC, EXT_HORIZ_TOTAL, par->ext_horiz_total);
814 i740outreg(par, VGA_CRT_IC, EXT_HORIZ_BLANK, par->ext_horiz_blank);
815 i740outreg(par, VGA_CRT_IC, EXT_OFFSET, par->ext_offset);
816 i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI, par->ext_start_addr_hi);
817 i740outreg(par, VGA_CRT_IC, EXT_START_ADDR, par->ext_start_addr);
819 i740outreg_mask(par, VGA_CRT_IC, INTERLACE_CNTL,
820 par->interlace_cntl, INTERLACE_ENABLE);
821 i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F);
822 i740outreg_mask(par, XRX, BITBLT_CNTL, par->bitblt_cntl, COLEXP_MODE);
823 i740outreg_mask(par, XRX, DISPLAY_CNTL,
824 par->display_cntl, VGA_WRAP_MODE | GUI_MODE);
825 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B);
826 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C);
828 i740outreg(par, XRX, PLL_CNTL, par->pll_cntl);
830 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_1,
831 par->pixelpipe_cfg1, DISPLAY_COLOR_MODE);
833 itemp = readl(par->regs + FWATER_BLC);
835 itemp |= par->lmi_fifo_watermark;
836 writel(itemp, par->regs + FWATER_BLC);
838 i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_60HZ);
840 i740outreg_mask(par, MRX, COL_KEY_CNTL_1, 0, BLANK_DISP_OVERLAY);
841 i740outreg_mask(par, XRX, IO_CTNL,
842 par->io_cntl, EXTENDED_ATTR_CNTL | EXTENDED_CRTC_CNTL);
844 if (par->pixelpipe_cfg1 != DISPLAY_8BPP_MODE) {
845 i740outb(par, VGA_PEL_MSK, 0xFF);
846 i740outb(par, VGA_PEL_IW, 0x00);
848 itemp = (par->pixelpipe_cfg0 & DAC_8_BIT) ? i : i >> 2;
849 i740outb(par, VGA_PEL_D, itemp);
850 i740outb(par, VGA_PEL_D, itemp);
851 i740outb(par, VGA_PEL_D, itemp);
857 vga_unprotect(par);
882 i740outb(info->par, VGA_PEL_IW, regno);
883 i740outb(info->par, VGA_PEL_D, red >> 8);
884 i740outb(info->par, VGA_PEL_D, green >> 8);
885 i740outb(info->par, VGA_PEL_D, blue >> 8);
908 struct i740fb_par *par = info->par;
935 par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
936 par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8;
937 par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
938 par->ext_start_addr =
941 i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_LO, base & 0x000000FF);
942 i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_HI,
944 i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI,
946 i740outreg(par, VGA_CRT_IC, EXT_START_ADDR,
954 struct i740fb_par *par = info->par;
981 i740outb(par, SRX, 0x01);
982 SEQ01 |= i740inb(par, SRX + 1) & ~0x20;
983 i740outb(par, SRX, 0x01);
984 i740outb(par, SRX + 1, SEQ01);
987 i740outreg(par, XRX, DPMS_SYNC_SELECT, DPMSSyncSelect);
1010 struct i740fb_par *par;
1023 par = info->par;
1024 mutex_init(&par->open_lock);
1029 info->pseudo_palette = par->pseudo_palette;
1050 par->regs = pci_ioremap_bar(dev, 1);
1051 if (!par->regs) {
1058 if ((i740inreg(par, XRX, DRAM_ROW_TYPE) & DRAM_ROW_1)
1060 i740outb(par, XRX, DRAM_ROW_BNDRY_1);
1062 i740outb(par, XRX, DRAM_ROW_BNDRY_0);
1063 info->screen_size = i740inb(par, XRX + 1) * 1024 * 1024;
1065 tmp = i740inreg(par, XRX, DRAM_ROW_CNTL_LO);
1066 par->has_sgram = !((tmp & DRAM_RAS_TIMING) ||
1071 par->has_sgram ? "SGRAM" : "SDRAM");
1081 par->ddc_registered = true;
1082 edid = fb_ddc_read(&par->ddc_adapter);
1148 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
1156 if (par->ddc_registered)
1157 i2c_del_adapter(&par->ddc_adapter);
1158 pci_iounmap(dev, par->regs);
1175 struct i740fb_par *par = info->par;
1176 arch_phys_wc_del(par->wc_cookie);
1179 if (par->ddc_registered)
1180 i2c_del_adapter(&par->ddc_adapter);
1181 pci_iounmap(dev, par->regs);
1192 struct i740fb_par *par = info->par;
1195 mutex_lock(&(par->open_lock));
1198 if (par->ref_count == 0) {
1199 mutex_unlock(&(par->open_lock));
1206 mutex_unlock(&(par->open_lock));
1215 struct i740fb_par *par = info->par;
1218 mutex_lock(&(par->open_lock));
1220 if (par->ref_count == 0)
1227 mutex_unlock(&(par->open_lock));