Lines Matching refs:XRX
129 i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SCL, DDC_SCL);
130 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL);
137 i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SDA, DDC_SDA);
138 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA);
145 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL);
147 return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SCL);
154 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA);
156 return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SDA);
756 i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_DISABLE);
760 i740outreg(par, XRX, VCLK2_VCO_M, par->video_clk2_m);
761 i740outreg(par, XRX, VCLK2_VCO_N, par->video_clk2_n);
762 i740outreg(par, XRX, VCLK2_VCO_MN_MSBS, par->video_clk2_mn_msbs);
763 i740outreg(par, XRX, VCLK2_VCO_DIV_SEL, par->video_clk2_div_sel);
765 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0,
821 i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F);
822 i740outreg_mask(par, XRX, BITBLT_CNTL, par->bitblt_cntl, COLEXP_MODE);
823 i740outreg_mask(par, XRX, DISPLAY_CNTL,
825 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B);
826 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C);
828 i740outreg(par, XRX, PLL_CNTL, par->pll_cntl);
830 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_1,
838 i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_60HZ);
841 i740outreg_mask(par, XRX, IO_CTNL,
987 i740outreg(par, XRX, DPMS_SYNC_SELECT, DPMSSyncSelect);
1058 if ((i740inreg(par, XRX, DRAM_ROW_TYPE) & DRAM_ROW_1)
1060 i740outb(par, XRX, DRAM_ROW_BNDRY_1);
1062 i740outb(par, XRX, DRAM_ROW_BNDRY_0);
1063 info->screen_size = i740inb(par, XRX + 1) * 1024 * 1024;
1065 tmp = i740inreg(par, XRX, DRAM_ROW_CNTL_LO);