Lines Matching defs:par
142 #define readreg(par, reg) readl((par)->regs + (reg))
143 #define writereg(par, reg, val) writel((val), (par)->regs + (reg))
237 static int calc_pll(int period_ps, struct gxt4500_par *par)
255 intf = m * par->refclk_ps;
261 t = par->refclk_ps * m * postdiv / n;
264 par->pll_m = m;
265 par->pll_n = n;
266 par->pll_pd1 = pdiv1;
267 par->pll_pd2 = pdiv2;
278 static int calc_pixclock(struct gxt4500_par *par)
280 return par->refclk_ps * par->pll_m * par->pll_pd1 * par->pll_pd2
281 / par->pll_n;
285 struct gxt4500_par *par)
294 if (calc_pll(var->pixclock, par) < 0)
300 par->pixfmt = DFA_PIX_32BIT;
302 par->pixfmt = DFA_PIX_24BIT;
305 par->pixfmt = DFA_PIX_24BIT;
309 par->pixfmt = DFA_PIX_16BIT_1555;
311 par->pixfmt = DFA_PIX_16BIT_565;
314 par->pixfmt = DFA_PIX_8BIT;
364 struct gxt4500_par par;
367 par = *(struct gxt4500_par *)info->par;
368 err = gxt4500_var_to_par(var, &par);
370 var->pixclock = calc_pixclock(&par);
371 gxt4500_unpack_pixfmt(var, par.pixfmt);
378 struct gxt4500_par *par = info->par;
387 save_par = *par;
388 err = gxt4500_var_to_par(var, par);
390 *par = save_par;
395 ctrlreg = readreg(par, DTG_CONTROL);
397 writereg(par, DTG_CONTROL, ctrlreg);
400 tmp = readreg(par, PLL_C) & ~0x7f;
401 if (par->pll_n < 38)
403 if (par->pll_n < 69)
405 else if (par->pll_n < 100)
409 writereg(par, PLL_C, tmp);
410 writereg(par, PLL_M, mdivtab[par->pll_m - 1]);
411 writereg(par, PLL_N, ndivtab[par->pll_n - 2]);
412 tmp = ((8 - par->pll_pd2) << 3) | (8 - par->pll_pd1);
413 if (par->pll_pd1 == 8 || par->pll_pd2 == 8) {
415 writereg(par, PLL_POSTDIV, tmp | 0x9);
418 writereg(par, PLL_POSTDIV, tmp);
422 writereg(par, CURSOR_MODE, CURSOR_MODE_OFF);
425 writereg(par, CTRL_REG0, CR0_RASTER_RESET | (CR0_RASTER_RESET << 16));
427 writereg(par, CTRL_REG0, CR0_RASTER_RESET << 16);
432 writereg(par, DTG_HORIZ_EXTENT, htot - 1);
433 writereg(par, DTG_HORIZ_DISPLAY, var->xres - 1);
434 writereg(par, DTG_HSYNC_START, var->xres + var->right_margin - 1);
435 writereg(par, DTG_HSYNC_END,
437 writereg(par, DTG_HSYNC_END_COMP,
439 writereg(par, DTG_VERT_EXTENT,
442 writereg(par, DTG_VERT_DISPLAY, var->yres - 1);
443 writereg(par, DTG_VSYNC_START, var->yres + var->lower_margin - 1);
444 writereg(par, DTG_VSYNC_END,
449 writereg(par, DTG_VERT_SHORT, htot - prefetch_pix - 1);
451 writereg(par, DTG_CONTROL, ctrlreg);
469 writereg(par, FB_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
470 writereg(par, REFRESH_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
471 writereg(par, FB_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
472 writereg(par, REFRESH_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
473 writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset);
474 writereg(par, REFRESH_SIZE, (var->xres << 16) | var->yres);
478 pixfmt = par->pixfmt;
480 writereg(par, DFA_FB_A, dfa_ctl);
488 writereg(par, WAT_FMT + (i << 4), watfmt[pixfmt]);
489 writereg(par, WAT_CMAP_OFFSET + (i << 4), 0);
490 writereg(par, WAT_CTRL + (i << 4), 0);
491 writereg(par, WAT_GAMMA_CTRL + (i << 4), WAT_GAMMA_DISABLE);
495 ctrlreg = readreg(par, SYNC_CTL) &
504 writereg(par, SYNC_CTL, ctrlreg);
518 struct gxt4500_par *par = info->par;
524 writereg(par, CMAP + reg * 4, cmap_entry);
526 if (reg < 16 && par->pixfmt != DFA_PIX_8BIT) {
529 switch (par->pixfmt) {
552 struct gxt4500_par *par = info->par;
560 writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset);
566 struct gxt4500_par *par = info->par;
569 ctrl = readreg(par, SYNC_CTL);
571 dctl = readreg(par, DISP_CTL);
588 writereg(par, SYNC_CTL, ctrl);
589 writereg(par, DISP_CTL, dctl);
618 struct gxt4500_par *par;
652 par = info->par;
654 par->refclk_ps = cardinfo[cardtype].refclk_ps;
658 info->pseudo_palette = par->pseudo_palette;
661 par->regs = pci_ioremap_bar(pdev, 0);
662 if (!par->regs) {
677 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
724 iounmap(par->regs);
738 struct gxt4500_par *par;
742 par = info->par;
744 arch_phys_wc_del(par->wc_cookie);
746 iounmap(par->regs);