Lines Matching refs:cinfo
381 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
382 static void WGen(const struct cirrusfb_info *cinfo,
384 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
385 static void AttrOn(const struct cirrusfb_info *cinfo);
386 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
387 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
388 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
389 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
392 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
421 static inline int is_laguna(const struct cirrusfb_info *cinfo)
423 return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
451 struct cirrusfb_info *cinfo = info->par;
452 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
478 struct cirrusfb_info *cinfo = info->par;
484 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
485 cinfo->multiplexing = 0;
502 switch (cinfo->btype) {
507 cinfo->multiplexing = 1;
511 cinfo->multiplexing = 1;
521 cinfo->doubleVCLK = 0;
522 if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ &&
524 cinfo->doubleVCLK = 1;
536 struct cirrusfb_info *cinfo = info->par;
627 if (!is_laguna(cinfo))
635 struct cirrusfb_info *cinfo = info->par;
638 assert(cinfo != NULL);
639 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
645 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
649 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
651 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
661 struct cirrusfb_info *cinfo = info->par;
663 u8 __iomem *regbase = cinfo->regbase;
698 bi = &cirrusfb_board_info[cinfo->btype];
736 if (cinfo->multiplexing) {
839 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64)
841 if (cinfo->multiplexing)
843 if (cinfo->doubleVCLK)
856 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 ||
857 cinfo->btype == BT_SD64) {
866 if (is_laguna(cinfo)) {
867 long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
868 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
871 if (cinfo->btype == BT_LAGUNAB) {
872 tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
874 fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4);
877 fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
878 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
879 control = fb_readw(cinfo->laguna_mmio + 0x402);
880 threshold = fb_readw(cinfo->laguna_mmio + 0xea);
890 if ((cinfo->btype == BT_SD64) ||
891 (cinfo->btype == BT_ALPINE) ||
892 (cinfo->btype == BT_GD5480))
896 if (is_laguna(cinfo)) {
927 WGen(cinfo, VGA_MIS_W, tmp);
946 switch (cinfo->btype) {
955 cinfo->multiplexing ?
971 switch (cinfo->btype) {
999 WGen(cinfo, VGA_PEL_MSK, 0x01);
1000 if (cinfo->multiplexing)
1002 WHDR(cinfo, 0x4a);
1005 WHDR(cinfo, 0);
1020 switch (cinfo->btype) {
1029 cinfo->multiplexing ?
1045 switch (cinfo->btype) {
1073 if (cinfo->multiplexing)
1075 WHDR(cinfo, 0x4a);
1078 WHDR(cinfo, 0);
1089 switch (cinfo->btype) {
1108 cinfo->doubleVCLK ? 0xa3 : 0xa7);
1133 WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1);
1136 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1148 switch (cinfo->btype) {
1191 WHDR(cinfo, 0xc5);
1215 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
1218 if (is_laguna(cinfo)) {
1242 AttrOn(cinfo);
1244 if (is_laguna(cinfo)) {
1246 fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
1247 fb_writew(format, cinfo->laguna_mmio + 0xc0);
1248 fb_writew(threshold, cinfo->laguna_mmio + 0xea);
1281 struct cirrusfb_info *cinfo = info->par;
1298 cinfo->pseudo_palette[regno] = v;
1303 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1320 struct cirrusfb_info *cinfo = info->par;
1339 if (!is_laguna(cinfo))
1340 cirrusfb_WaitBLT(cinfo->regbase);
1343 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
1344 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);
1347 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
1356 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
1359 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
1360 tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
1361 if (is_laguna(cinfo))
1365 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
1373 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1392 struct cirrusfb_info *cinfo = info->par;
1393 int current_mode = cinfo->blank_mode;
1412 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
1413 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
1434 vga_wgfx(cinfo->regbase, CL_GRE, val);
1436 cinfo->blank_mode = blank_mode;
1449 struct cirrusfb_info *cinfo = info->par;
1452 assert(cinfo != NULL);
1454 bi = &cirrusfb_board_info[cinfo->btype];
1457 switch (cinfo->btype) {
1459 WSFR(cinfo, 0x01);
1461 WSFR(cinfo, 0x51);
1465 WSFR2(cinfo, 0xff);
1470 WSFR(cinfo, 0x1f);
1472 WSFR(cinfo, 0x4f);
1477 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1480 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1484 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1488 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1508 if (cinfo->btype != BT_PICASSO4) {
1509 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1510 WGen(cinfo, CL_POS102, 0x01);
1511 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1513 if (cinfo->btype != BT_SD64)
1514 WGen(cinfo, CL_VSSM2, 0x01);
1517 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
1520 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1523 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1525 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1527 switch (cinfo->btype) {
1529 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1537 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1541 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1542 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1547 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1549 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1551 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1555 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1557 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1561 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1563 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1565 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1567 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1570 if (cinfo->btype != BT_PICASSO4) {
1572 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1574 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1578 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1580 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1582 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1584 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
1586 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
1589 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
1592 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
1595 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
1597 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
1599 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
1601 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
1603 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
1605 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
1607 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
1609 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
1611 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1613 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 ||
1614 is_laguna(cinfo))
1616 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1621 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
1623 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1624 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1625 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1627 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
1628 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1631 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
1632 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1633 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1634 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1635 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1636 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1637 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1638 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1639 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1640 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1641 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1642 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1643 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1644 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1645 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1646 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1649 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
1651 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
1653 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
1655 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
1657 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1660 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1662 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1665 WHDR(cinfo, 0); /* Hidden DAC register: - */
1669 static void switch_monitor(struct cirrusfb_info *cinfo, int on)
1674 if (cinfo->btype == BT_PICASSO4)
1676 if (cinfo->btype == BT_ALPINE)
1678 if (cinfo->btype == BT_GD5480)
1680 if (cinfo->btype == BT_PICASSO) {
1682 WSFR(cinfo, 0xff);
1686 switch (cinfo->btype) {
1688 WSFR(cinfo, cinfo->SFR | 0x21);
1691 WSFR(cinfo, cinfo->SFR | 0x28);
1694 WSFR(cinfo, 0x6f);
1699 switch (cinfo->btype) {
1701 WSFR(cinfo, cinfo->SFR & 0xde);
1704 WSFR(cinfo, cinfo->SFR & 0xd7);
1707 WSFR(cinfo, 0x4f);
1722 struct cirrusfb_info *cinfo = info->par;
1724 if (!is_laguna(cinfo)) {
1725 while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03)
1736 struct cirrusfb_info *cinfo = info->par;
1739 cinfo->pseudo_palette[region->color] : region->color;
1762 cirrusfb_RectFill(cinfo->regbase,
1775 struct cirrusfb_info *cinfo = info->par;
1803 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
1814 struct cirrusfb_info *cinfo = info->par;
1822 else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) &&
1839 cirrusfb_RectFill(cinfo->regbase,
1847 cirrusfb_RectFill(cinfo->regbase,
1868 struct cirrusfb_info *cinfo = info->par;
1870 if (is_laguna(cinfo)) {
1896 if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0)
1930 struct cirrusfb_info *cinfo = info->par;
1932 if (cinfo->laguna_mmio == NULL)
1933 iounmap(cinfo->laguna_mmio);
1947 struct cirrusfb_info *cinfo = info->par;
1953 iounmap(cinfo->regbase);
1977 struct cirrusfb_info *cinfo = info->par;
1980 info->pseudo_palette = cinfo->pseudo_palette;
1986 if (noaccel || is_laguna(cinfo)) {
1994 if (cinfo->btype == BT_GD5480) {
2002 strscpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2025 struct cirrusfb_info *cinfo = info->par;
2029 assert(cinfo->btype != BT_NONE);
2069 struct cirrusfb_info *cinfo = info->par;
2071 switch_monitor(cinfo, 0);
2075 cinfo->unmap(info);
2083 struct cirrusfb_info *cinfo;
2104 cinfo = info->par;
2105 cinfo->btype = (enum cirrus_board) ent->driver_data;
2109 (unsigned long long)pdev->resource[0].start, cinfo->btype);
2117 cinfo->regbase = NULL;
2118 cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000);
2123 board_size = (cinfo->btype == BT_GD5480) ?
2124 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
2151 cinfo->unmap = cirrusfb_pci_unmap;
2172 if (cinfo->laguna_mmio != NULL)
2173 iounmap(cinfo->laguna_mmio);
2203 struct cirrusfb_info *cinfo;
2251 cinfo = info->par;
2252 cinfo->btype = btype;
2255 cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024)
2257 if (!cinfo->regbase) {
2273 cinfo->unmap = cirrusfb_zorro_unmap;
2281 vga_wseq(cinfo->regbase, CL_SEQR1F,
2300 iounmap(cinfo->regbase);
2410 static void WGen(const struct cirrusfb_info *cinfo,
2415 if (cinfo->btype == BT_PICASSO) {
2423 vga_w(cinfo->regbase, regofs + regnum, val);
2427 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2431 if (cinfo->btype == BT_PICASSO) {
2439 return vga_r(cinfo->regbase, regofs + regnum);
2443 static void AttrOn(const struct cirrusfb_info *cinfo)
2445 assert(cinfo != NULL);
2447 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2450 vga_w(cinfo->regbase, VGA_ATT_IW,
2451 vga_r(cinfo->regbase, VGA_ATT_R));
2454 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2455 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2458 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2467 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2469 if (is_laguna(cinfo))
2471 if (cinfo->btype == BT_PICASSO) {
2474 WGen(cinfo, VGA_PEL_MSK, 0x00);
2477 RGen(cinfo, VGA_PEL_IW);
2482 RGen(cinfo, VGA_PEL_MSK);
2484 RGen(cinfo, VGA_PEL_MSK);
2486 RGen(cinfo, VGA_PEL_MSK);
2488 RGen(cinfo, VGA_PEL_MSK);
2491 WGen(cinfo, VGA_PEL_MSK, val);
2494 if (cinfo->btype == BT_PICASSO) {
2496 RGen(cinfo, VGA_PEL_IW);
2501 WGen(cinfo, VGA_PEL_MSK, 0xff);
2507 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2510 assert(cinfo->regbase != NULL);
2511 cinfo->SFR = val;
2512 z_writeb(val, cinfo->regbase + 0x8000);
2517 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2522 assert(cinfo->regbase != NULL);
2523 cinfo->SFR = val;
2524 z_writeb(val, cinfo->regbase + 0x9000);
2529 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2535 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2537 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2538 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
2539 cinfo->btype == BT_SD64 || is_laguna(cinfo)) {
2541 if (cinfo->btype == BT_PICASSO)
2543 vga_w(cinfo->regbase, data, red);
2544 vga_w(cinfo->regbase, data, green);
2545 vga_w(cinfo->regbase, data, blue);
2547 vga_w(cinfo->regbase, data, blue);
2548 vga_w(cinfo->regbase, data, green);
2549 vga_w(cinfo->regbase, data, red);
2555 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2560 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2562 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2563 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2564 if (cinfo->btype == BT_PICASSO)
2566 *red = vga_r(cinfo->regbase, data);
2567 *green = vga_r(cinfo->regbase, data);
2568 *blue = vga_r(cinfo->regbase, data);
2570 *blue = vga_r(cinfo->regbase, data);
2571 *green = vga_r(cinfo->regbase, data);
2572 *red = vga_r(cinfo->regbase, data);