Lines Matching refs:rinfo
281 void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
283 if (rinfo->no_schedule || oops_in_progress)
289 void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo)
291 /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */
296 void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo)
298 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
300 _radeon_msleep(rinfo, 5);
302 if (rinfo->errata & CHIP_ERRATA_R300_CG) {
312 void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask)
317 spin_lock_irqsave(&rinfo->reg_lock, flags);
322 spin_unlock_irqrestore(&rinfo->reg_lock, flags);
325 u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
330 radeon_pll_errata_after_index(rinfo);
332 radeon_pll_errata_after_data(rinfo);
336 void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val)
339 radeon_pll_errata_after_index(rinfo);
341 radeon_pll_errata_after_data(rinfo);
344 void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
349 tmp = __INPLL(rinfo, index);
352 __OUTPLL(rinfo, index, tmp);
355 void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
367 void radeon_engine_flush(struct radeonfb_info *rinfo)
378 _radeon_fifo_wait(rinfo, 64);
389 void _radeon_engine_idle(struct radeonfb_info *rinfo)
394 _radeon_fifo_wait(rinfo, 64);
398 radeon_engine_flush(rinfo);
408 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
410 if (!rinfo->bios_seg)
412 pci_unmap_rom(dev, rinfo->bios_seg);
415 static int radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
438 pci_name(rinfo->pdev));
442 rinfo->bios_seg = rom;
448 pci_name(rinfo->pdev), BIOS_IN16(0));
480 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
500 rinfo->fp_bios_start = BIOS_IN16(0x48);
504 rinfo->bios_seg = NULL;
505 radeon_unmap_ROM(rinfo, dev);
510 static int radeon_find_mem_vbios(struct radeonfb_info *rinfo)
533 rinfo->bios_seg = rom_base;
534 rinfo->fp_bios_start = BIOS_IN16(0x48);
545 static int radeon_read_xtal_OF(struct radeonfb_info *rinfo)
547 struct device_node *dp = rinfo->of_node;
558 rinfo->pll.ref_clk = (*val) / 10;
562 rinfo->pll.sclk = (*val) / 10;
566 rinfo->pll.mclk = (*val) / 10;
575 static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
644 radeon_pll_errata_after_index(rinfo);
698 rinfo->pll.ref_clk = xtal;
699 rinfo->pll.ref_div = ref_div;
700 rinfo->pll.sclk = sclk;
701 rinfo->pll.mclk = mclk;
709 static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
716 switch (rinfo->chipset) {
719 rinfo->pll.ppll_max = 35000;
720 rinfo->pll.ppll_min = 12000;
721 rinfo->pll.mclk = 23000;
722 rinfo->pll.sclk = 23000;
723 rinfo->pll.ref_clk = 2700;
730 rinfo->pll.ppll_max = 35000;
731 rinfo->pll.ppll_min = 12000;
732 rinfo->pll.mclk = 27500;
733 rinfo->pll.sclk = 27500;
734 rinfo->pll.ref_clk = 2700;
740 rinfo->pll.ppll_max = 35000;
741 rinfo->pll.ppll_min = 12000;
742 rinfo->pll.mclk = 25000;
743 rinfo->pll.sclk = 25000;
744 rinfo->pll.ref_clk = 2700;
750 rinfo->pll.ppll_max = 40000;
751 rinfo->pll.ppll_min = 20000;
752 rinfo->pll.mclk = 27000;
753 rinfo->pll.sclk = 27000;
754 rinfo->pll.ref_clk = 2700;
761 rinfo->pll.ppll_max = 35000;
762 rinfo->pll.ppll_min = 12000;
763 rinfo->pll.mclk = 16600;
764 rinfo->pll.sclk = 16600;
765 rinfo->pll.ref_clk = 2700;
768 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
775 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
785 if (!force_measure_pll && rinfo->bios_seg) {
786 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
788 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
789 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
790 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
791 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
792 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
793 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
803 if (radeon_probe_pll_params(rinfo) == 0) {
819 if (rinfo->pll.mclk == 0)
820 rinfo->pll.mclk = 20000;
821 if (rinfo->pll.sclk == 0)
822 rinfo->pll.sclk = 20000;
825 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
826 rinfo->pll.ref_div,
827 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
828 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
829 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
834 struct radeonfb_info *rinfo = info->par;
839 if (radeon_match_mode(rinfo, &v, var))
917 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
925 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
950 struct radeonfb_info *rinfo = info->par;
956 if (rinfo->asleep)
969 struct radeonfb_info *rinfo = info->par;
981 if (!rinfo->is_mobility)
1018 if (!rinfo->is_mobility)
1038 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
1044 if (rinfo->lock_blank)
1073 switch (rinfo->mon1_type) {
1085 del_timer_sync(&rinfo->lvds_timer);
1089 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
1096 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1097 rinfo->init_state.lvds_gen_cntl |=
1100 radeon_msleep(rinfo->panel_info.pwr_delay);
1104 rinfo->pending_lvds_gen_cntl = target_val;
1105 mod_timer(&rinfo->lvds_timer,
1107 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1122 if (rinfo->is_mobility || rinfo->is_IGP)
1130 rinfo->pending_lvds_gen_cntl = val;
1131 mod_timer(&rinfo->lvds_timer,
1133 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1134 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1135 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1136 if (rinfo->is_mobility || rinfo->is_IGP)
1151 struct radeonfb_info *rinfo = info->par;
1153 if (rinfo->asleep)
1156 return radeon_screen_blank(rinfo, blank, 0);
1161 struct radeonfb_info *rinfo)
1173 rinfo->palette[regno].red = red;
1174 rinfo->palette[regno].green = green;
1175 rinfo->palette[regno].blue = blue;
1180 if (!rinfo->asleep) {
1183 if (rinfo->bpp == 16) {
1186 if (rinfo->depth == 16 && regno > 63)
1188 if (rinfo->depth == 15 && regno > 31)
1194 if (rinfo->depth == 16) {
1197 (rinfo->palette[regno>>1].red << 16) |
1199 (rinfo->palette[regno>>1].blue));
1200 green = rinfo->palette[regno<<1].green;
1204 if (rinfo->depth != 16 || regno < 32) {
1211 u32 *pal = rinfo->info->pseudo_palette;
1212 switch (rinfo->depth) {
1235 struct radeonfb_info *rinfo = info->par;
1239 if (!rinfo->asleep) {
1240 if (rinfo->is_mobility) {
1247 if (rinfo->has_CRTC2) {
1254 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1256 if (!rinfo->asleep && rinfo->is_mobility)
1264 struct radeonfb_info *rinfo = info->par;
1269 if (!rinfo->asleep) {
1270 if (rinfo->is_mobility) {
1277 if (rinfo->has_CRTC2) {
1299 rinfo);
1304 if (!rinfo->asleep && rinfo->is_mobility)
1310 static void radeon_save_state (struct radeonfb_info *rinfo,
1341 radeon_pll_errata_after_index(rinfo);
1347 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1354 if (rinfo->is_mobility) {
1371 radeon_pll_errata_after_index(rinfo);
1372 radeon_pll_errata_after_data(rinfo);
1389 radeon_pll_errata_after_index(rinfo);
1390 radeon_pll_errata_after_data(rinfo);
1393 if (IS_R300_VARIANT(rinfo) ||
1394 rinfo->family == CHIP_FAMILY_RS300 ||
1395 rinfo->family == CHIP_FAMILY_RS400 ||
1396 rinfo->family == CHIP_FAMILY_RS480) {
1446 struct radeonfb_info *rinfo = from_timer(rinfo, t, lvds_timer);
1450 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1457 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1461 int primary_mon = PRIMARY_MONITOR(rinfo);
1467 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1494 radeon_write_pll_regs(rinfo, mode);
1510 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1521 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1556 while (rinfo->has_CRTC2) {
1567 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) {
1589 if (freq > rinfo->pll.ppll_max)
1590 freq = rinfo->pll.ppll_max;
1591 if (freq*12 < rinfo->pll.ppll_min)
1592 freq = rinfo->pll.ppll_min / 12;
1594 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1603 if (pll_output_freq >= rinfo->pll.ppll_min &&
1604 pll_output_freq <= rinfo->pll.ppll_max)
1615 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1625 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1628 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1629 rinfo->pll.ref_clk);
1630 regs->ppll_ref_div = rinfo->pll.ref_div;
1640 struct radeonfb_info *rinfo = info->par;
1652 int primary_mon = PRIMARY_MONITOR(rinfo);
1679 if (rinfo->panel_info.xres < mode->xres)
1680 mode->xres = rinfo->panel_info.xres;
1681 if (rinfo->panel_info.yres < mode->yres)
1682 mode->yres = rinfo->panel_info.yres;
1684 hTotal = mode->xres + rinfo->panel_info.hblank;
1685 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1686 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1688 vTotal = mode->yres + rinfo->panel_info.vblank;
1689 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1690 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1692 h_sync_pol = !rinfo->panel_info.hAct_high;
1693 v_sync_pol = !rinfo->panel_info.vAct_high;
1695 pixClock = 100000000 / rinfo->panel_info.clock;
1697 if (rinfo->panel_info.use_bios_dividers) {
1699 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1700 (rinfo->panel_info.post_divider << 16);
1701 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1737 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1769 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1773 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1817 rinfo->bpp = mode->bits_per_pixel;
1818 rinfo->depth = depth;
1828 radeon_calc_pll_regs(rinfo, newmode, freq);
1830 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1835 if (mode->xres > rinfo->panel_info.xres)
1836 mode->xres = rinfo->panel_info.xres;
1837 if (mode->yres > rinfo->panel_info.yres)
1838 mode->yres = rinfo->panel_info.yres;
1840 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1842 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1845 if (mode->xres != rinfo->panel_info.xres) {
1847 rinfo->panel_info.xres);
1858 if (mode->yres != rinfo->panel_info.yres) {
1860 rinfo->panel_info.yres);
1870 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1884 if (IS_R300_VARIANT(rinfo) ||
1885 (rinfo->family == CHIP_FAMILY_R200)) {
1894 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1895 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1896 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1897 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1907 if (IS_R300_VARIANT(rinfo) ||
1908 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1915 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1917 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1919 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1921 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1926 if (!rinfo->asleep) {
1927 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1928 radeon_write_mode (rinfo, newmode, 0);
1931 radeonfb_engine_init (rinfo);
1935 info->fix.line_length = rinfo->pitch*64;
1939 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1944 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1945 rinfo->depth, info->fix.line_length);
1969 static int radeon_set_fbinfo(struct radeonfb_info *rinfo)
1971 struct fb_info *info = rinfo->info;
1973 info->par = rinfo;
1974 info->pseudo_palette = rinfo->pseudo_palette;
1980 info->screen_base = rinfo->fb_base;
1981 info->screen_size = rinfo->mapped_vram;
1983 strscpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1984 info->fix.smem_start = rinfo->fb_base_phys;
1985 info->fix.smem_len = rinfo->video_ram;
1992 info->fix.mmio_start = rinfo->mmio_base_phys;
2017 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
2025 if (rinfo->has_CRTC2) {
2043 rinfo->fb_local_base = aper_base;
2046 rinfo->fb_local_base = 0;
2067 if (rinfo->has_CRTC2)
2072 if (rinfo->has_CRTC2)
2081 if (rinfo->has_CRTC2)
2092 static void radeon_identify_vram(struct radeonfb_info *rinfo)
2097 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2098 (rinfo->family == CHIP_FAMILY_RS200) ||
2099 (rinfo->family == CHIP_FAMILY_RS300) ||
2100 (rinfo->family == CHIP_FAMILY_RC410) ||
2101 (rinfo->family == CHIP_FAMILY_RS400) ||
2102 (rinfo->family == CHIP_FAMILY_RS480) ) {
2115 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2116 (rinfo->family == CHIP_FAMILY_RS200)) {
2128 rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK;
2134 if (rinfo->video_ram == 0) {
2135 switch (rinfo->pdev->device) {
2138 rinfo->video_ram = 8192 * 1024;
2149 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2151 rinfo->vram_ddr = 1;
2153 rinfo->vram_ddr = 0;
2156 if (IS_R300_VARIANT(rinfo)) {
2159 case 0: rinfo->vram_width = 64; break;
2160 case 1: rinfo->vram_width = 128; break;
2161 case 2: rinfo->vram_width = 256; break;
2162 default: rinfo->vram_width = 128; break;
2164 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2165 (rinfo->family == CHIP_FAMILY_RS100) ||
2166 (rinfo->family == CHIP_FAMILY_RS200)){
2168 rinfo->vram_width = 32;
2170 rinfo->vram_width = 64;
2173 rinfo->vram_width = 128;
2175 rinfo->vram_width = 64;
2183 pci_name(rinfo->pdev),
2184 rinfo->video_ram / 1024,
2185 rinfo->vram_ddr ? "DDR" : "SDRAM",
2186 rinfo->vram_width);
2205 struct radeonfb_info *rinfo = info->par;
2207 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2217 struct radeonfb_info *rinfo = info->par;
2219 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2244 struct radeonfb_info *rinfo;
2264 rinfo = info->par;
2265 rinfo->info = info;
2266 rinfo->pdev = pdev;
2268 spin_lock_init(&rinfo->reg_lock);
2269 timer_setup(&rinfo->lvds_timer, radeon_lvds_timer_func, 0);
2274 snprintf(rinfo->name, sizeof(rinfo->name),
2277 snprintf(rinfo->name, sizeof(rinfo->name),
2280 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2281 rinfo->chipset = pdev->device;
2282 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2283 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2284 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2287 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2288 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2298 pci_name(rinfo->pdev));
2305 pci_name(rinfo->pdev));
2310 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2311 if (!rinfo->mmio_base) {
2313 pci_name(rinfo->pdev));
2318 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2323 rinfo->errata = 0;
2324 if (rinfo->family == CHIP_FAMILY_R300 &&
2327 rinfo->errata |= CHIP_ERRATA_R300_CG;
2329 if (rinfo->family == CHIP_FAMILY_RV200 ||
2330 rinfo->family == CHIP_FAMILY_RS200)
2331 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2333 if (rinfo->family == CHIP_FAMILY_RV100 ||
2334 rinfo->family == CHIP_FAMILY_RS100 ||
2335 rinfo->family == CHIP_FAMILY_RS200)
2336 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2342 rinfo->of_node = pci_device_to_OF_node(pdev);
2343 if (rinfo->of_node == NULL)
2345 pci_name(rinfo->pdev));
2353 fixup_memory_mappings(rinfo);
2357 radeon_identify_vram(rinfo);
2359 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2362 rinfo->fb_base = ioremap_wc(rinfo->fb_base_phys,
2363 rinfo->mapped_vram);
2364 } while (rinfo->fb_base == NULL &&
2365 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM));
2367 if (rinfo->fb_base == NULL) {
2369 pci_name(rinfo->pdev));
2374 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2375 rinfo->mapped_vram/1024);
2388 if (!rinfo->is_mobility)
2389 radeon_map_ROM(rinfo, pdev);
2398 if (rinfo->bios_seg == NULL)
2399 radeon_find_mem_vbios(rinfo);
2405 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2406 radeon_map_ROM(rinfo, pdev);
2409 radeon_get_pllinfo(rinfo);
2413 radeon_create_i2c_busses(rinfo);
2417 radeon_set_fbinfo (rinfo);
2420 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2423 radeon_check_modes(rinfo, mode_option);
2426 if (rinfo->mon1_EDID)
2427 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2429 if (rinfo->mon2_EDID)
2430 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2439 radeon_save_state (rinfo, &rinfo->init_state);
2440 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2447 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2449 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2457 pci_name(rinfo->pdev));
2462 rinfo->wc_cookie = arch_phys_wc_add(rinfo->fb_base_phys,
2463 rinfo->video_ram);
2466 radeonfb_bl_init(rinfo);
2468 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2470 if (rinfo->bios_seg)
2471 radeon_unmap_ROM(rinfo, pdev);
2476 iounmap(rinfo->fb_base);
2478 kfree(rinfo->mon1_EDID);
2479 kfree(rinfo->mon2_EDID);
2480 if (rinfo->mon1_modedb)
2481 fb_destroy_modedb(rinfo->mon1_modedb);
2484 radeon_delete_i2c_busses(rinfo);
2486 if (rinfo->bios_seg)
2487 radeon_unmap_ROM(rinfo, pdev);
2488 iounmap(rinfo->mmio_base);
2505 struct radeonfb_info *rinfo = info->par;
2507 if (!rinfo)
2510 radeonfb_pm_exit(rinfo);
2512 if (rinfo->mon1_EDID)
2513 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2514 if (rinfo->mon2_EDID)
2515 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2517 del_timer_sync(&rinfo->lvds_timer);
2518 arch_phys_wc_del(rinfo->wc_cookie);
2519 radeonfb_bl_exit(rinfo);
2522 iounmap(rinfo->mmio_base);
2523 iounmap(rinfo->fb_base);
2528 kfree(rinfo->mon1_EDID);
2529 kfree(rinfo->mon2_EDID);
2530 if (rinfo->mon1_modedb)
2531 fb_destroy_modedb(rinfo->mon1_modedb);
2533 radeon_delete_i2c_busses(rinfo);