Lines Matching refs:ct
254 if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))
256 if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))
258 /*aty_calc_pll_ct(info, &pll->ct);*/
266 ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
268 if(pll->ct.xres > 0) {
270 ret /= pll->ct.xres;
293 pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl);
297 par->clk_wr_offset, pll->ct.vclk_fb_div,
298 pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real);
315 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
321 tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2);
328 tmp |= pll->ct.pll_ext_cntl;
333 aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par);
335 aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par);
338 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par);
341 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
342 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
360 aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par);
361 aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par);
385 pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;
387 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU;
388 pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
389 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
390 pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
392 pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par);
393 pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par);
396 pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
397 pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
410 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
411 pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07;
412 pll->ct.xclk_ref_div = 1;
413 switch (pll->ct.xclk_post_div) {
418 pll->ct.xclk_ref_div = 3;
419 pll->ct.xclk_post_div = 0;
423 printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div);
426 pll->ct.mclk_fb_mult = 2;
427 if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) {
428 pll->ct.mclk_fb_mult = 4;
429 pll->ct.xclk_post_div -= 1;
434 __func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div);
440 pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2;
441 pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2;
444 pll->ct.fifo_size = 32;
446 pll->ct.fifo_size = 24;
447 pll->ct.xclkpagefaultdelay += 2;
448 pll->ct.xclkmaxrasdelay += 3;
454 pll->ct.dsp_loop_latency = 10;
456 pll->ct.dsp_loop_latency = 8;
457 pll->ct.xclkpagefaultdelay += 2;
463 pll->ct.dsp_loop_latency = 9;
465 pll->ct.dsp_loop_latency = 8;
466 pll->ct.xclkpagefaultdelay += 1;
471 pll->ct.dsp_loop_latency = 11;
473 pll->ct.dsp_loop_latency = 10;
474 pll->ct.xclkpagefaultdelay += 1;
478 pll->ct.dsp_loop_latency = 8;
479 pll->ct.xclkpagefaultdelay += 3;
482 pll->ct.dsp_loop_latency = 11;
483 pll->ct.xclkpagefaultdelay += 3;
487 if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay)
488 pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1;
497 pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16;
506 pll->ct.fifo_size = 32;
508 pll->ct.fifo_size = 24;
515 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
517 pll->ct.xclk_post_div_real = aty_postdividers[pll_ext_cntl & 0x07];
521 pll->ct.mclk_fb_div = mclk_fb_div;
525 pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
528 q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
529 (pll->ct.mclk_fb_mult * par->xclk_per);
539 pll->ct.xclk_post_div_real = aty_postdividers[xpost_div];
540 pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8;
545 pll->ct.xclk_post_div = xpost_div;
546 pll->ct.xclk_ref_div = 1;
551 pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) /
552 (par->ref_clk_per * pll->ct.pll_ref_div);
554 __func__, pllmclk, pllmclk / pll->ct.xclk_post_div_real);
558 pll->ct.pll_gen_cntl = OSC_EN;
560 pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */;
563 pll->ct.pll_ext_cntl = 0;
565 pll->ct.pll_ext_cntl = xpost_div;
567 if (pll->ct.mclk_fb_mult == 4)
568 pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B;
571 pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */
577 pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */
579 q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
589 pll->ct.sclk_fb_div = q * sclk_post_div_real / 8;
590 pll->ct.spll_cntl2 = mpost_div << 4;
592 pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) /
593 (par->ref_clk_per * pll->ct.pll_ref_div);
600 pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par);
601 pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC);
619 aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par);
620 aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par);
628 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
629 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
630 aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par);
631 aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par);
632 aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par);