Lines Matching defs:par
23 u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par)
27 aty_st_8(CLOCK_CNTL_ADDR, (offset << 2) & PLL_ADDR, par);
29 return aty_ld_8(CLOCK_CNTL_DATA, par);
32 static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par)
35 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par);
37 aty_st_8(CLOCK_CNTL_DATA, val & PLL_DATA, par);
38 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par);
141 struct atyfb_par *par = (struct atyfb_par *) info->par;
143 multiplier = multiplier * par->lcd_width;
146 ras_multiplier = ras_multiplier * par->lcd_width;
210 struct atyfb_par *par = (struct atyfb_par *) info->par;
214 q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per;
227 (par->ref_clk_per * pll->pll_ref_div);
235 if (par->pll_limits.ecp_max) {
239 while (ecp > par->pll_limits.ecp_max && ecp_div < 2) {
251 struct atyfb_par *par = (struct atyfb_par *) info->par;
264 struct atyfb_par *par = (struct atyfb_par *) info->par;
266 ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
269 ret *= par->lcd_width;
281 struct atyfb_par *par = (struct atyfb_par *) info->par;
297 par->clk_wr_offset, pll->ct.vclk_fb_div,
301 if (par->lcd_table != 0) {
303 lcd_gen_cntrl = aty_ld_lcd(LCD_GEN_CNTL, par);
304 aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl & ~LCD_ON, par);
307 aty_st_8(CLOCK_CNTL, par->clk_wr_offset | CLOCK_STROBE, par);
310 crtc_gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
312 aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_EXT_DISP_EN, par);
315 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
318 tmp2 = par->clk_wr_offset << 1;
319 tmp = aty_ld_pll_ct(VCLK_POST_DIV, par);
322 aty_st_pll_ct(VCLK_POST_DIV, tmp, par);
325 tmp = aty_ld_pll_ct(PLL_EXT_CNTL, par);
326 tmp &= ~(0x10U << par->clk_wr_offset);
329 aty_st_pll_ct(PLL_EXT_CNTL, tmp, par);
332 tmp = VCLK0_FB_DIV + par->clk_wr_offset;
333 aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par);
335 aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par);
338 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par);
341 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
342 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
347 aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl, par);
354 else if (par->ram_type >= SDRAM)
358 aty_st_pll_ct(DLL_CNTL, dll_cntl, par);
359 aty_st_pll_ct(VFC_CNTL, 0x1b, par);
360 aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par);
361 aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par);
364 aty_st_pll_ct(DLL_CNTL, dll_cntl, par);
366 aty_st_pll_ct(DLL_CNTL, dll_cntl | 0x40, par);
368 aty_st_pll_ct(DLL_CNTL, dll_cntl & ~0x40, par);
371 if (par->lcd_table != 0) {
373 aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl, par);
380 struct atyfb_par *par = (struct atyfb_par *) info->par;
383 clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
385 pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;
387 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU;
388 pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
389 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
390 pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
392 pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par);
393 pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par);
396 pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
397 pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
403 struct atyfb_par *par = (struct atyfb_par *) info->par;
410 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
437 memcntl = aty_ld_le32(MEM_CNTL, par);
451 switch (par->ram_type) {
491 dsp_config = aty_ld_le32(DSP_CONFIG, par);
492 aty_ld_le32(DSP_ON_OFF, par);
493 aty_ld_le32(VGA_DSP_CONFIG, par);
494 aty_ld_le32(VGA_DSP_ON_OFF, par);
513 if (par->mclk_per == 0) {
515 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
516 pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
518 mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
525 pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
528 q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
529 (pll->ct.mclk_fb_mult * par->xclk_per);
552 (par->ref_clk_per * pll->ct.pll_ref_div);
557 if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM))
570 if (par->mclk_per == par->xclk_per) {
579 q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
593 (par->ref_clk_per * pll->ct.pll_ref_div);
600 pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par);
609 struct atyfb_par *par = info->par;
611 if (par->mclk_per != par->xclk_per) {
619 aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par);
620 aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par);
628 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
629 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
630 aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par);
631 aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par);
632 aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par);