Lines Matching refs:vgabase
152 svga_tilecursor(par->state.vgabase, info, cursor);
460 regval = vga_rseq(par->state.vgabase, 0x1C);
463 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
464 code[1] = vga_r(par->state.vgabase, dac_regs[code[0] & 3]);
469 vga_wseq(par->state.vgabase, 0x1C, regval);
479 regval = vga_rseq(par->state.vgabase, 0x1C);
482 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
483 vga_w(par->state.vgabase, dac_regs[code[0] & 3], code[1]);
488 vga_wseq(par->state.vgabase, 0x1C, regval);
504 regval = vga_r(par->state.vgabase, VGA_MIS_R);
505 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
517 void __iomem *vgabase = par->state.vgabase;
520 par->state.vgabase = vgabase;
650 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
653 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
654 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
657 svga_set_default_gfx_regs(par->state.vgabase);
658 svga_set_default_atc_regs(par->state.vgabase);
659 svga_set_default_seq_regs(par->state.vgabase);
660 svga_set_default_crt_regs(par->state.vgabase);
661 svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF);
662 svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0);
665 svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
666 svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
668 vga_wseq(par->state.vgabase, 0x13, info->fix.smem_start >> 16);
669 vga_wseq(par->state.vgabase, 0x14, info->fix.smem_start >> 24);
670 vga_wseq(par->state.vgabase, 0x15, 0);
671 vga_wseq(par->state.vgabase, 0x16, 0);
676 vga_wseq(par->state.vgabase, 0x18, regval);
680 svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value);
683 svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08);
686 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
688 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
691 svga_wcrt_mask(par->state.vgabase, 0x44, 0x04, 0x04);
693 svga_wcrt_mask(par->state.vgabase, 0x44, 0x00, 0x04);
703 svga_set_textmode_vga_regs(par->state.vgabase);
705 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
706 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
712 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
714 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
715 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
721 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
722 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
728 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */
732 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
736 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
744 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
745 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
751 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
752 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
758 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */
759 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
767 vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */
768 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
783 svga_set_timings(par->state.vgabase, &ark_timing_regs, &(info->var), hmul, hdiv,
791 vga_wcrt(par->state.vgabase, 0x42, (value + 1) / 2);
797 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
798 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
873 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
874 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
878 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
879 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
885 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
886 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
912 svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, offset);
1011 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
1014 regval = vga_rseq(par->state.vgabase, 0x10);