Lines Matching defs:CMD1
42 #define CMD1(x, x1) ((1 << 30) | ((x) << 9) | 0x100 | (x1))
59 CMD1(0xB0, 0x16), /* Wake */
67 CMD1(0xB0, 0x00), /* Deep stand by in */
72 CMD1(0xB0, 0x16),
73 CMD1(0xBC, 0x80),
74 CMD1(0xE1, 0x00),
75 CMD1(0x36, 0x50),
76 CMD1(0x3B, 0x00),
81 CMD1(0xB0, 0x16),
82 CMD1(0xBC, 0x81),
83 CMD1(0xE1, 0x00),
84 CMD1(0x36, 0x50),
85 CMD1(0x3B, 0x22),
90 CMD1(0xcf, 0x02), /* Blanking period control (1) */
92 CMD1(0xd1, 0x01), /* CKV timing control on/off */
96 CMD1(0xd5, 0x14), /* ASW timing control (2) */
103 CMD1(0xd6, 0x02), /* Blanking period control (1) */
105 CMD1(0xd8, 0x01), /* CKV timing control on/off */
109 CMD1(0xe0, 0x0a), /* ASW timing control (2) */
116 CMD1(0xB0, 0x16),
117 CMD1(0xBC, 0x80),
118 CMD1(0xE1, 0x00),
119 CMD1(0x3B, 0x00),
124 CMD1(0xB0, 0x16),
125 CMD1(0xBC, 0x81),
126 CMD1(0xE1, 0x00),
127 CMD1(0x3B, 0x22),
132 CMD1(0xcf, 0x02), /* Blanking period control (1) */
134 CMD1(0xd1, 0x01), /* CKV timing control on/off */
138 CMD1(0xd5, 0x28), /* ASW timing control (2) */
147 CMD1(0xba, 0x01), /* Display mode (1) */
148 CMD1(0xbb, 0x00), /* Display mode (2) */
149 CMD1(0x3a, 0x60), /* Display mode 18-bit RGB */
150 CMD1(0xbf, 0x10), /* Drive system change control */
151 CMD1(0xb1, 0x56), /* Booster operation setup */
152 CMD1(0xb2, 0x33), /* Booster mode setup */
153 CMD1(0xb3, 0x11), /* Booster frequency setup */
154 CMD1(0xb4, 0x02), /* Op amp/system clock */
155 CMD1(0xb5, 0x35), /* VCS voltage */
156 CMD1(0xb6, 0x40), /* VCOM voltage */
157 CMD1(0xb7, 0x03), /* External display signal */
158 CMD1(0xbd, 0x00), /* ASW slew rate */
159 CMD1(0xbe, 0x00), /* Dummy data for QuadData operation */
160 CMD1(0xc0, 0x11), /* Sleep out FR count (A) */
161 CMD1(0xc1, 0x11), /* Sleep out FR count (B) */
162 CMD1(0xc2, 0x11), /* Sleep out FR count (C) */
166 CMD1(0xc6, 0xc0), /* Sleep out FR count (G) */
168 CMD1(0xc8, 0x44), /* Gamma 1 fine tuning (2) */
169 CMD1(0xc9, 0x33), /* Gamma 1 inclination adjustment */
170 CMD1(0xca, 0x00), /* Gamma 1 blue offset adjustment */