Lines Matching defs:ltv350qv_write_reg
36 static int ltv350qv_write_reg(struct ltv350qv *lcd, u8 reg, u16 val)
72 if (ltv350qv_write_reg(lcd, LTV_PWRCTL1, 0x0000))
77 if (ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE))
79 if (ltv350qv_write_reg(lcd, LTV_PWRCTL2, LTV_VCOML_ENABLE))
83 if (ltv350qv_write_reg(lcd, LTV_PWRCTL1,
91 ret = ltv350qv_write_reg(lcd, LTV_IFCTL,
93 ret |= ltv350qv_write_reg(lcd, LTV_DATACTL,
96 ret |= ltv350qv_write_reg(lcd, LTV_ENTRY_MODE,
102 ret |= ltv350qv_write_reg(lcd, LTV_GATECTL1, LTV_CLW(3));
103 ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
105 ret |= ltv350qv_write_reg(lcd, LTV_VBP, 0x000a);
106 ret |= ltv350qv_write_reg(lcd, LTV_HBP, 0x0021);
107 ret |= ltv350qv_write_reg(lcd, LTV_SOTCTL, LTV_SDT(3) | LTV_EQ(0));
108 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(0), 0x0103);
109 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(1), 0x0301);
110 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(2), 0x1f0f);
111 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(3), 0x1f0f);
112 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(4), 0x0707);
113 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(5), 0x0307);
114 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(6), 0x0707);
115 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(7), 0x0000);
116 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(8), 0x0004);
117 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(9), 0x0000);
125 ret = ltv350qv_write_reg(lcd, LTV_PWRCTL1,
129 ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
143 ltv350qv_write_reg(lcd, LTV_PWRCTL1,
146 ltv350qv_write_reg(lcd, LTV_GATECTL2,
151 ltv350qv_write_reg(lcd, LTV_PWRCTL2, 0x0000);
154 ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE);
163 ret = ltv350qv_write_reg(lcd, LTV_PWRCTL1,
167 ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
171 ret |= ltv350qv_write_reg(lcd, LTV_PWRCTL2, 0x0000);
177 ret |= ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE);