Lines Matching refs:vdev
112 int (*readfn)(struct vfio_pci_core_device *vdev, int pos, int count,
114 int (*writefn)(struct vfio_pci_core_device *vdev, int pos, int count,
175 static int vfio_default_config_read(struct vfio_pci_core_device *vdev, int pos,
181 memcpy(val, vdev->vconfig + pos, count);
187 struct pci_dev *pdev = vdev->pdev;
201 static int vfio_default_config_write(struct vfio_pci_core_device *vdev, int pos,
218 memcpy(&virt_val, vdev->vconfig + pos, count);
223 memcpy(vdev->vconfig + pos, &virt_val, count);
228 struct pci_dev *pdev = vdev->pdev;
248 static int vfio_direct_config_read(struct vfio_pci_core_device *vdev, int pos,
254 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
260 memcpy(val, vdev->vconfig + pos, count);
263 memcpy(val, vdev->vconfig + pos,
266 memcpy(val, vdev->vconfig + pos, 1);
273 static int vfio_raw_config_write(struct vfio_pci_core_device *vdev, int pos,
279 ret = vfio_user_config_write(vdev->pdev, pos, val, count);
286 static int vfio_raw_config_read(struct vfio_pci_core_device *vdev, int pos,
292 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
300 static int vfio_virt_config_write(struct vfio_pci_core_device *vdev, int pos,
304 memcpy(vdev->vconfig + pos, &val, count);
308 static int vfio_virt_config_read(struct vfio_pci_core_device *vdev, int pos,
312 memcpy(val, vdev->vconfig + pos, count);
400 bool __vfio_pci_memory_enabled(struct vfio_pci_core_device *vdev)
402 struct pci_dev *pdev = vdev->pdev;
403 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
420 static void vfio_bar_restore(struct vfio_pci_core_device *vdev)
422 struct pci_dev *pdev = vdev->pdev;
423 u32 *rbar = vdev->rbar;
437 if (vdev->nointx) {
467 static void vfio_bar_fixup(struct vfio_pci_core_device *vdev)
469 struct pci_dev *pdev = vdev->pdev;
474 if (!vdev->bardirty)
477 vbar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
499 vbar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];
518 vdev->bardirty = false;
521 static int vfio_basic_config_read(struct vfio_pci_core_device *vdev, int pos,
526 vfio_bar_fixup(vdev);
528 count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
531 if (offset == PCI_COMMAND && vdev->pdev->no_command_memory) {
532 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
543 static bool vfio_need_bar_restore(struct vfio_pci_core_device *vdev)
549 if (vdev->rbar[i]) {
550 ret = pci_user_read_config_dword(vdev->pdev, pos, &bar);
551 if (ret || vdev->rbar[i] != bar)
559 static int vfio_basic_config_write(struct vfio_pci_core_device *vdev, int pos,
563 struct pci_dev *pdev = vdev->pdev;
568 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND];
589 vfio_pci_zap_and_down_write_memory_lock(vdev);
591 down_write(&vdev->memory_lock);
605 vfio_need_bar_restore(vdev))
606 vfio_bar_restore(vdev);
609 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
612 up_write(&vdev->memory_lock);
626 up_write(&vdev->memory_lock);
636 if (virt_intx_disable && !vdev->virq_disabled) {
637 vdev->virq_disabled = true;
638 vfio_pci_intx_mask(vdev);
639 } else if (!virt_intx_disable && vdev->virq_disabled) {
640 vdev->virq_disabled = false;
641 vfio_pci_intx_unmask(vdev);
646 vdev->bardirty = true;
703 static void vfio_lock_and_set_power_state(struct vfio_pci_core_device *vdev,
707 vfio_pci_zap_and_down_write_memory_lock(vdev);
709 down_write(&vdev->memory_lock);
711 vfio_pci_set_power_state(vdev, state);
712 up_write(&vdev->memory_lock);
715 static int vfio_pm_config_write(struct vfio_pci_core_device *vdev, int pos,
719 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
741 vfio_lock_and_set_power_state(vdev, state);
787 static int vfio_vpd_config_write(struct vfio_pci_core_device *vdev, int pos,
791 struct pci_dev *pdev = vdev->pdev;
792 __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR);
793 __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA);
802 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
869 static int vfio_exp_config_write(struct vfio_pci_core_device *vdev, int pos,
873 __le16 *ctrl = (__le16 *)(vdev->vconfig + pos -
877 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
893 ret = pci_user_read_config_dword(vdev->pdev,
898 vfio_pci_zap_and_down_write_memory_lock(vdev);
899 pci_try_reset_function(vdev->pdev);
900 up_write(&vdev->memory_lock);
920 readrq = max(readrq, pcie_get_mps(vdev->pdev));
922 pcie_set_readrq(vdev->pdev, readrq);
953 static int vfio_af_config_write(struct vfio_pci_core_device *vdev, int pos,
957 u8 *ctrl = vdev->vconfig + pos - offset + PCI_AF_CTRL;
959 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
975 ret = pci_user_read_config_byte(vdev->pdev,
980 vfio_pci_zap_and_down_write_memory_lock(vdev);
981 pci_try_reset_function(vdev->pdev);
982 up_write(&vdev->memory_lock);
1113 static int vfio_find_cap_start(struct vfio_pci_core_device *vdev, int pos)
1118 cap = vdev->pci_config_map[pos];
1124 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap)
1130 static int vfio_msi_config_read(struct vfio_pci_core_device *vdev, int pos,
1139 start = vfio_find_cap_start(vdev, pos);
1141 flags = (__le16 *)&vdev->vconfig[start];
1144 *flags |= cpu_to_le16(vdev->msi_qmax << 1);
1147 return vfio_default_config_read(vdev, pos, count, perm, offset, val);
1150 static int vfio_msi_config_write(struct vfio_pci_core_device *vdev, int pos,
1154 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
1164 start = vfio_find_cap_start(vdev, pos);
1166 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS];
1171 if (vdev->irq_type != VFIO_PCI_MSI_IRQ_INDEX)
1175 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) {
1177 flags |= vdev->msi_qmax << 4;
1182 ret = pci_user_write_config_word(vdev->pdev,
1229 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
1230 static int vfio_msi_cap_len(struct vfio_pci_core_device *vdev, u8 pos)
1232 struct pci_dev *pdev = vdev->pdev;
1246 if (vdev->msi_perm)
1249 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL_ACCOUNT);
1250 if (!vdev->msi_perm)
1253 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);
1255 kfree(vdev->msi_perm);
1263 static int vfio_vc_cap_len(struct vfio_pci_core_device *vdev, u16 pos)
1265 struct pci_dev *pdev = vdev->pdev;
1304 static int vfio_cap_len(struct vfio_pci_core_device *vdev, u8 cap, u8 pos)
1306 struct pci_dev *pdev = vdev->pdev;
1314 return vfio_msi_cap_len(vdev, pos);
1325 vdev->extended_caps = (dword != 0);
1341 vdev->extended_caps = (dword != 0);
1379 static int vfio_ext_cap_len(struct vfio_pci_core_device *vdev, u16 ecap, u16 epos)
1381 struct pci_dev *pdev = vdev->pdev;
1396 return vfio_vc_cap_len(vdev, epos);
1458 static void vfio_update_pm_vconfig_bytes(struct vfio_pci_core_device *vdev,
1461 __le16 *pmc = (__le16 *)&vdev->vconfig[offset + PCI_PM_PMC];
1462 __le16 *ctrl = (__le16 *)&vdev->vconfig[offset + PCI_PM_CTRL];
1469 static int vfio_fill_vconfig_bytes(struct vfio_pci_core_device *vdev,
1472 struct pci_dev *pdev = vdev->pdev;
1484 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset];
1493 __le16 *wordp = (__le16 *)&vdev->vconfig[offset];
1502 u8 *byte = &vdev->vconfig[offset];
1516 static int vfio_cap_init(struct vfio_pci_core_device *vdev)
1518 struct pci_dev *pdev = vdev->pdev;
1519 u8 *map = vdev->pci_config_map;
1537 prev = &vdev->vconfig[PCI_CAPABILITY_LIST];
1562 len = vfio_cap_len(vdev, cap, pos);
1588 ret = vfio_fill_vconfig_bytes(vdev, pos, len);
1593 vfio_update_pm_vconfig_bytes(vdev, pos);
1595 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT];
1602 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS];
1609 static int vfio_ecap_init(struct vfio_pci_core_device *vdev)
1611 struct pci_dev *pdev = vdev->pdev;
1612 u8 *map = vdev->pci_config_map;
1617 if (!vdev->extended_caps)
1639 len = vfio_ext_cap_len(vdev, ecap, epos);
1681 ret = vfio_fill_vconfig_bytes(vdev, epos, len);
1692 *(__le32 *)&vdev->vconfig[epos] &=
1697 prev = (__le32 *)&vdev->vconfig[epos];
1702 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;
1729 int vfio_config_init(struct vfio_pci_core_device *vdev)
1731 struct pci_dev *pdev = vdev->pdev;
1751 vdev->pci_config_map = map;
1752 vdev->vconfig = vconfig;
1758 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF);
1762 vdev->bardirty = true;
1770 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
1771 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]);
1772 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);
1773 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]);
1774 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]);
1775 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]);
1776 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);
1812 if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx)
1815 ret = vfio_cap_init(vdev);
1819 ret = vfio_ecap_init(vdev);
1827 vdev->pci_config_map = NULL;
1829 vdev->vconfig = NULL;
1833 void vfio_config_free(struct vfio_pci_core_device *vdev)
1835 kfree(vdev->vconfig);
1836 vdev->vconfig = NULL;
1837 kfree(vdev->pci_config_map);
1838 vdev->pci_config_map = NULL;
1839 if (vdev->msi_perm) {
1840 free_perm_bits(vdev->msi_perm);
1841 kfree(vdev->msi_perm);
1842 vdev->msi_perm = NULL;
1850 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_core_device *vdev,
1853 u8 cap = vdev->pci_config_map[pos];
1856 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++)
1862 static ssize_t vfio_config_do_rw(struct vfio_pci_core_device *vdev, char __user *buf,
1865 struct pci_dev *pdev = vdev->pdev;
1880 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos));
1890 cap_id = vdev->pci_config_map[*ppos];
1903 cap_start = vfio_find_cap_start(vdev, *ppos);
1910 perm = vdev->msi_perm;
1913 cap_start = vfio_find_cap_start(vdev, *ppos);
1929 ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
1932 ret = perm->readfn(vdev, *ppos, count,
1945 ssize_t vfio_pci_config_rw(struct vfio_pci_core_device *vdev, char __user *buf,
1955 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite);