Lines Matching refs:res
269 MLX5_SET(tisc, tisc, transport_domain, ndev->res.tdn);
270 err = mlx5_vdpa_create_tis(mvdev, in, &ndev->res.tisn);
279 mlx5_vdpa_destroy_tis(&ndev->mvdev, ndev->res.tisn);
361 MLX5_SET(create_qp_in, in, uid, ndev->mvdev.res.uid);
375 MLX5_SET(qpc, qpc, pd, ndev->mvdev.res.pdn);
377 MLX5_SET(qpc, qpc, uar_page, ndev->mvdev.res.uar->index);
431 MLX5_SET(qpc, qpc, pd, ndev->mvdev.res.pdn);
441 vqp->mqp.uid = ndev->mvdev.res.uid;
465 MLX5_SET(destroy_qp_in, in, uid, ndev->mvdev.res.uid);
512 void __iomem *uar_page = ndev->mvdev.res.uar->map;
539 void __iomem *uar_page = ndev->mvdev.res.uar->map;
571 MLX5_SET(create_cq_in, in, uid, ndev->mvdev.res.uid);
587 MLX5_SET(cqc, cqc, uar_page, ndev->mvdev.res.uar->index);
722 MLX5_SET(create_umem_in, in, uid, ndev->mvdev.res.uid);
884 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, uid, ndev->mvdev.res.uid);
897 MLX5_SET(virtio_net_q_object, obj_context, tisn_or_qpn, ndev->res.tisn);
921 MLX5_SET(virtio_q, vq_ctx, pd, ndev->mvdev.res.pdn);
950 MLX5_SET(destroy_virtio_net_q_in, in, general_obj_out_cmd_hdr.uid, ndev->mvdev.res.uid);
987 MLX5_SET(qp_2rst_in, *in, uid, ndev->mvdev.res.uid);
999 MLX5_SET(rst2init_qp_in, *in, uid, ndev->mvdev.res.uid);
1016 MLX5_SET(init2rtr_qp_in, *in, uid, ndev->mvdev.res.uid);
1034 MLX5_SET(rtr2rts_qp_in, *in, uid, ndev->mvdev.res.uid);
1139 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, uid, ndev->mvdev.res.uid);
1195 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, uid, ndev->mvdev.res.uid);
1223 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, uid, ndev->mvdev.res.uid);
1244 MLX5_SET(destroy_virtio_q_counters_in, in, hdr.uid, ndev->mvdev.res.uid);
1422 MLX5_SET(create_rqt_in, in, uid, ndev->mvdev.res.uid);
1432 err = mlx5_vdpa_create_rqt(&ndev->mvdev, in, inlen, &ndev->res.rqtn);
1457 MLX5_SET(modify_rqt_in, in, uid, ndev->mvdev.res.uid);
1467 err = mlx5_vdpa_modify_rqt(&ndev->mvdev, in, inlen, ndev->res.rqtn);
1477 mlx5_vdpa_destroy_rqt(&ndev->mvdev, ndev->res.rqtn);
1500 MLX5_SET(create_tir_in, in, uid, ndev->mvdev.res.uid);
1514 MLX5_SET(tirc, tirc, indirect_table, ndev->res.rqtn);
1515 MLX5_SET(tirc, tirc, transport_domain, ndev->res.tdn);
1517 err = mlx5_vdpa_create_tir(&ndev->mvdev, in, &ndev->res.tirn);
1529 mlx5_vdpa_destroy_tir(&ndev->mvdev, ndev->res.tirn);
1615 dests[0].tir_num = ndev->res.tirn;
2104 iowrite16(idx, ndev->mvdev.res.kick_addr);
3027 addr = (phys_addr_t)ndev->mvdev.res.phys_kick_addr;
3078 MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, uid, ndev->mvdev.res.uid);
3240 struct mlx5_vdpa_net_resources *res = &ndev->res;
3243 if (res->valid) {
3248 err = mlx5_vdpa_alloc_transport_domain(&ndev->mvdev, &res->tdn);
3256 res->valid = true;
3261 mlx5_vdpa_dealloc_transport_domain(&ndev->mvdev, res->tdn);
3267 struct mlx5_vdpa_net_resources *res = &ndev->res;
3269 if (!res->valid)
3273 mlx5_vdpa_dealloc_transport_domain(&ndev->mvdev, res->tdn);
3274 res->valid = false;