Lines Matching refs:fact
151 #define CH341_CLK_DIV(ps, fact) (1 << (12 - 3 * (ps) - (fact)))
168 * baudrate = 48000000 / (2^(12 - 3 * ps - fact) * div), where
171 * 0 <= fact <= 1,
172 * 2 <= div <= 256 if fact = 0, or
173 * 9 <= div <= 256 if fact = 1
177 unsigned int fact, div, clk_div;
188 * Start with highest possible base clock (fact = 1) that will give a
191 fact = 1;
201 clk_div = CH341_CLK_DIV(ps, fact);
208 /* Halve base clock (fact = 0) if required. */
212 fact = 0;
227 * Prefer lower base clock (fact = 0) if even divisor.
231 if (fact == 1 && div % 2 == 0) {
233 fact = 0;
236 return (0x100 - div) << 8 | fact << 2 | ps;