Lines Matching refs:config
328 struct tegra_utmip_config *config = phy->config;
348 val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
349 val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
350 val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
485 struct tegra_utmip_config *config = phy->config;
506 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
507 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
512 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
578 if (!config->xcvr_setup_use_fuses) {
579 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
580 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
582 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
583 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
587 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
588 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
595 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
604 if (config->xcvr_setup_use_fuses)
1183 struct tegra_utmip_config *config;
1206 tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
1208 if (!tegra_phy->config)
1211 config = tegra_phy->config;
1214 &config->hssync_start_delay);
1219 &config->elastic_limit);
1224 &config->idle_wait_delay);
1229 &config->term_range_adj);
1234 &config->xcvr_lsfslew);
1239 &config->xcvr_lsrslew);
1245 &config->xcvr_hsslew);
1250 &config->hssquelch_level);
1255 &config->hsdiscon_level);
1260 config->xcvr_setup_use_fuses = of_property_read_bool(
1263 if (!config->xcvr_setup_use_fuses) {
1265 &config->xcvr_setup);