Lines Matching refs:musb_readl
55 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
57 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
75 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
76 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
78 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
79 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
81 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
82 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
84 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
85 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
87 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
106 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
107 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
115 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
116 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
117 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
124 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
125 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
212 val = musb_readl(fifo, 0);
220 val = musb_readl(fifo, 0);
307 val = musb_readl(fifo, 0);
349 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
372 reg = musb_readl(tbase, TUSB_PRCM_CONF);
413 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
437 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
438 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
448 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
568 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
569 conf = musb_readl(tbase, TUSB_DEV_CONF);
586 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
622 musb_readl(tbase, TUSB_DEV_OTG_STAT),
638 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
639 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
640 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
641 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
673 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
685 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
834 int_mask = musb_readl(tbase, TUSB_INT_MASK);
837 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
856 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
865 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
891 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
899 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
960 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
1052 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1085 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1089 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);