Lines Matching defs:tbase
51 void __iomem *tbase = musb->ctrl_base;
55 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
57 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
68 void __iomem *tbase = musb->ctrl_base;
75 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
76 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
78 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
79 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
81 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
82 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
84 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
85 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
87 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
101 void __iomem *tbase = musb->ctrl_base;
106 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
107 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
110 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
113 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
115 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
116 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
117 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
120 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
122 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
124 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
125 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
333 void __iomem *tbase = musb->ctrl_base;
349 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
357 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
369 void __iomem *tbase = musb->ctrl_base;
372 reg = musb_readl(tbase, TUSB_PRCM_CONF);
383 musb_writel(tbase, TUSB_PRCM_CONF, reg);
396 void __iomem *tbase = musb->ctrl_base;
406 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
413 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
423 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
433 void __iomem *tbase = musb->ctrl_base;
437 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
438 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
447 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
448 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
449 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
558 void __iomem *tbase = musb->ctrl_base;
568 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
569 conf = musb_readl(tbase, TUSB_DEV_CONF);
586 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
614 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
615 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
616 musb_writel(tbase, TUSB_DEV_CONF, conf);
622 musb_readl(tbase, TUSB_DEV_OTG_STAT),
635 void __iomem *tbase = musb->ctrl_base;
638 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
639 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
640 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
641 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
667 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
669 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
671 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
673 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
683 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
685 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
827 void __iomem *tbase = musb->ctrl_base;
834 int_mask = musb_readl(tbase, TUSB_INT_MASK);
835 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
837 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
854 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
855 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
856 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
865 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
866 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
884 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
891 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
894 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
899 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
901 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
913 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
918 musb_writel(tbase, TUSB_INT_MASK, int_mask);
933 void __iomem *tbase = musb->ctrl_base;
937 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
940 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
941 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
942 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
945 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
946 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
947 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
950 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
954 musb_writel(tbase, TUSB_INT_CTRL_CONF,
960 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
962 musb_writel(tbase, TUSB_INT_SRC_SET,
977 void __iomem *tbase = musb->ctrl_base;
982 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
983 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
984 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
985 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
1002 void __iomem *tbase = musb->ctrl_base;
1008 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
1011 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1014 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1018 musb_writel(tbase, TUSB_DMA_REQ_CONF,
1024 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1030 void __iomem *tbase = musb->ctrl_base;
1052 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1068 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1076 musb_writel(tbase, TUSB_PRCM_MNGMT,
1085 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1087 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1089 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1091 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);