Lines Matching refs:mbase
73 static dma_addr_t read_txq_cur_addr(void __iomem *mbase, u8 epnum)
78 txcpr = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
79 txhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum));
84 static dma_addr_t read_rxq_cur_addr(void __iomem *mbase, u8 epnum)
89 rxcpr = mtu3_readl(mbase, USB_QMU_RQCPR(epnum));
90 rxhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum));
95 static void write_txq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma)
99 mtu3_writel(mbase, USB_QMU_TQSAR(epnum),
101 tqhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum));
104 mtu3_writel(mbase, USB_QMU_TQHIAR(epnum), tqhiar);
107 static void write_rxq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma)
111 mtu3_writel(mbase, USB_QMU_RQSAR(epnum),
113 rqhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum));
116 mtu3_writel(mbase, USB_QMU_RQHIAR(epnum), rqhiar);
192 void __iomem *mbase = mtu->mac_base;
198 mtu3_writel(mbase, offset, QMU_Q_RESUME);
199 if (!(mtu3_readl(mbase, offset) & QMU_Q_ACTIVE))
200 mtu3_writel(mbase, offset, QMU_Q_RESUME);
334 void __iomem *mbase = mtu->mac_base;
340 write_txq_start_addr(mbase, epnum, ring->dma);
341 mtu3_setbits(mbase, MU3D_EP_TXCR0(epnum), TX_DMAREQEN);
343 mtu3_setbits(mbase, U3D_QCR1, QMU_TX_ZLP(epnum));
344 mtu3_writel(mbase, U3D_TQERRIESR0,
347 if (mtu3_readl(mbase, USB_QMU_TQCSR(epnum)) & QMU_Q_ACTIVE) {
351 mtu3_writel(mbase, USB_QMU_TQCSR(epnum), QMU_Q_START);
354 write_rxq_start_addr(mbase, epnum, ring->dma);
355 mtu3_setbits(mbase, MU3D_EP_RXCR0(epnum), RX_DMAREQEN);
357 mtu3_clrbits(mbase, U3D_QCR3, QMU_RX_ZLP(epnum));
359 mtu3_setbits(mbase, U3D_QCR3, QMU_RX_COZ(epnum));
360 mtu3_writel(mbase, U3D_RQERRIESR0,
362 mtu3_writel(mbase, U3D_RQERRIESR1, QMU_RX_ZLP_ERR(epnum));
364 if (mtu3_readl(mbase, USB_QMU_RQCSR(epnum)) & QMU_Q_ACTIVE) {
368 mtu3_writel(mbase, USB_QMU_RQCSR(epnum), QMU_Q_START);
378 void __iomem *mbase = mtu->mac_base;
386 if (!(mtu3_readl(mbase, qcsr) & QMU_Q_ACTIVE)) {
390 mtu3_writel(mbase, qcsr, QMU_Q_STOP);
393 mtu3_setbits(mbase, MU3D_EP_TXCR0(epnum), TX_FLUSHFIFO);
395 ret = readl_poll_timeout_atomic(mbase + qcsr, value,
404 mtu3_setbits(mbase, MU3D_EP_TXCR0(epnum), TX_FLUSHFIFO);
429 void __iomem *mbase = mtu->mac_base;
440 cur_gpd_dma = read_txq_cur_addr(mbase, epnum);
451 mtu3_clrbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN);
453 ret = readl_poll_timeout_atomic(mbase + MU3D_EP_TXCR0(mep->epnum),
459 mtu3_setbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_TXPKTRDY);
466 mtu3_setbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN);
512 void __iomem *mbase = mtu->mac_base;
520 cur_gpd_dma = read_txq_cur_addr(mbase, epnum);
552 void __iomem *mbase = mtu->mac_base;
559 cur_gpd_dma = read_rxq_cur_addr(mbase, epnum);
600 void __iomem *mbase = mtu->mac_base;
605 errval = mtu3_readl(mbase, U3D_RQERRIR0);
606 mtu3_writel(mbase, U3D_RQERRIR0, errval);
621 errval = mtu3_readl(mbase, U3D_RQERRIR1);
626 mtu3_writel(mbase, U3D_RQERRIR1, errval);
630 errval = mtu3_readl(mbase, U3D_TQERRIR0);
638 mtu3_writel(mbase, U3D_TQERRIR0, errval);
644 void __iomem *mbase = mtu->mac_base;
649 qmu_status = mtu3_readl(mbase, U3D_QISAR1);
650 qmu_status &= mtu3_readl(mbase, U3D_QIER1);
652 qmu_done_status = mtu3_readl(mbase, U3D_QISAR0);
653 qmu_done_status &= mtu3_readl(mbase, U3D_QIER0);
654 mtu3_writel(mbase, U3D_QISAR0, qmu_done_status); /* W1C */