Lines Matching refs:op_regs
94 halted = readl(&xhci->op_regs->status) & STS_HALT;
98 cmd = readl(&xhci->op_regs->command);
100 writel(cmd, &xhci->op_regs->command);
118 ret = xhci_handshake(&xhci->op_regs->status,
139 temp = readl(&xhci->op_regs->command);
143 writel(temp, &xhci->op_regs->command);
149 ret = xhci_handshake(&xhci->op_regs->status,
177 state = readl(&xhci->op_regs->status);
190 command = readl(&xhci->op_regs->command);
192 writel(command, &xhci->op_regs->command);
204 ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
217 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
259 val = readl(&xhci->op_regs->command);
261 writel(val, &xhci->op_regs->command);
264 val = readl(&xhci->op_regs->status);
266 writel(val, &xhci->op_regs->status);
269 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
271 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
272 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
274 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
292 err = xhci_handshake(&xhci->op_regs->status,
470 temp = readl(&xhci->op_regs->command);
472 writel(temp, &xhci->op_regs->command);
608 temp = readl(&xhci->op_regs->status);
609 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
617 readl(&xhci->op_regs->status));
664 readl(&xhci->op_regs->status));
673 xhci->s3.command = readl(&xhci->op_regs->command);
674 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
675 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
676 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
692 writel(xhci->s3.command, &xhci->op_regs->command);
693 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
694 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
695 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
708 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
717 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
815 status = readl(&xhci->op_regs->status);
894 command = readl(&xhci->op_regs->command);
896 writel(command, &xhci->op_regs->command);
901 if (xhci_handshake(&xhci->op_regs->status,
913 command = readl(&xhci->op_regs->command);
915 writel(command, &xhci->op_regs->command);
917 if (xhci_handshake(&xhci->op_regs->status,
928 res = readl(&xhci->op_regs->status);
999 retval = xhci_handshake(&xhci->op_regs->status,
1013 command = readl(&xhci->op_regs->command);
1015 writel(command, &xhci->op_regs->command);
1021 if (xhci_handshake(&xhci->op_regs->status,
1029 temp = readl(&xhci->op_regs->status);
1061 temp = readl(&xhci->op_regs->status);
1062 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1069 readl(&xhci->op_regs->status));
1095 command = readl(&xhci->op_regs->command);
1097 writel(command, &xhci->op_regs->command);
1098 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1673 temp = readl(&xhci->op_regs->status);
3869 state = readl(&xhci->op_regs->status);
4160 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
5161 xhci->op_regs = hcd->regs +