Lines Matching refs:ir_set
277 ARRAY_SIZE(xhci->run_regs->ir_set));
282 ir = &xhci->run_regs->ir_set[i];
303 if (!ir || !ir->ir_set)
306 iman = readl(&ir->ir_set->irq_pending);
307 writel(ER_IRQ_ENABLE(iman), &ir->ir_set->irq_pending);
316 if (!ir || !ir->ir_set)
319 iman = readl(&ir->ir_set->irq_pending);
320 writel(ER_IRQ_DISABLE(iman), &ir->ir_set->irq_pending);
522 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
529 temp = readl(&ir->ir_set->irq_control);
532 writel(temp, &ir->ir_set->irq_control);
681 ir->s3_erst_size = readl(&ir->ir_set->erst_size);
682 ir->s3_erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
683 ir->s3_erst_dequeue = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
684 ir->s3_irq_pending = readl(&ir->ir_set->irq_pending);
685 ir->s3_irq_control = readl(&ir->ir_set->irq_control);
696 writel(ir->s3_erst_size, &ir->ir_set->erst_size);
697 xhci_write_64(xhci, ir->s3_erst_base, &ir->ir_set->erst_base);
698 xhci_write_64(xhci, ir->s3_erst_dequeue, &ir->ir_set->erst_dequeue);
699 writel(ir->s3_irq_pending, &ir->ir_set->irq_pending);
700 writel(ir->s3_irq_control, &ir->ir_set->irq_control);